- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371670 > 83C795 (SMSC Corporation) Ethernet System Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁(yè)數(shù)： | 93/136頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)當(dāng)前第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
8.0
BUFFER STRUCTURING AND DATA
MOVEMENT PROCESSES
8.1
TRANSMIT PACKETS
8.1.1
A packet for transmission is placed by the host into
buffer memory. This packet must include the DA,
SA, and data fields. The preamble, SFD, and CRC
(normally) are not included in the buffer. If CRC
generation is suppressed, the CRC field for the
packet is also supplied by the host. The packet is
placed in a contiguous block of memory in the
buffer, starting on a 256-byte boundary.
Single Packet Transmission
Valid 802.3 packets have at least 48 bytes of data.
If less data is to be transmitted on an 802.3 network,
it is the responsibility of the host to build a packet
with pad data included. The 83C795 will transmit
frames of any programmed length (greater than 17
bytes), even those which are too short to be valid
frames in an 802.3 network. DMA will transfer the
number of bytes programmed into the TCNTH and
TCNTL Register pair starting from address
(TSTART * 100H).
8.1.2
To support multiple transmissions per command, a
transmit queue can be enabled by setting the
ALTEGO bit in the Enhancement Register (ENH.5).
In this mode, a table of frame descriptors defines
the starting location and length of all enqueued
transmissions. This descriptor table is processed in
a circular manner by the LAN controller.
Multiple Packet Transmissions
The table is treated as a ring of entries whose
starting and ending points are defined by a pair of
registers (TBEGIN and TE ND) in the LAN
controller. These registers are initialized with the
upper 8-bits of address for the first location of the
table and the first location after the end of the table.
TEND is not within the table. When table processing
reaches the location defined by TEND, it is switched
back to TBEGIN. The table must be aligned with
256 byte boundary in the buffer memory. Each entry
is 8 bytes long. The format of this buffering is
defined in Figure 8-1.
To send multiple transmissions, the driver builds the
frames in buffer memory in the same contiguous
form presently expected. The driver then adds an
entry for each frame into a table of transmit
descriptors. This entry contains the starting location
and length, and transmit configuration for each
frame in the transmit queue. Places are provided in
the table for return of the Transmit Status (TSTAT)
Register and collision count associated with each
transmission. A simple semaphore protocol will be
used to control ownership of transmit buffers.
The LAN controller keeps a pointer in the TTABH
and TTABL Registers to the transmit descriptor
table. This pointer is initialized by the driver when
the table is first built and should not need
re-initialization thereafter. When transmit command
has been set and device is online, transmit begins
from the entry pointed to by the TTABH and TTABL
Registers. The LAN controller first checks the
TSTAT field. If it encounters a field equal to FF, it
will attempt to transmit the frame pointed to by the
entry. The status field will be changed to zero after
the remainder of the entry has been read. When it
encounters a TSTAT field not equal to FF, no frame
will be sent, the transmit complete interrupt will be
sent and the field will not be altered.
If the frame is marked for transmission, the DMA
controller loads its TSTARTH, TSTARTL, TCNTH,
TCNTL, and TCON Registers from the descriptor.
TSTAT gets marked as having been opened by the
LAN controller and transmission proceeds as with
single transmissions except that when the
transmission has completed, the transmit status
and collision count are moved by DMA into the
table. The table pointer is updated and transmission
of next entry begins.
If a transmit abort occurs (too many collisions) the
transmitter will stop processing the chain and post
the current transmit and interrupt status. If the
CMD.STP bit is set, the transmission of any
ongoing frame proceeds until completion or abort
but no successive frames in the chain are
processed. The TTAB indices will point to the first
unprocessed frame in the table so that none are
lost.
An alternative mode of controlling the transmit
interrupt can be enabled by the EOTINT bit in the
Enhancement (ENH) Register. When enabled, the
transmit interrupt will be generated only upon
83C795
BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES
80
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84063 | The Constituents of Semiconductor Components |
| 8406601QA | CMOS Programmable Peripheral Interface |
| 8406601XA | CMOS Programmable Peripheral Interface |
| 8406602XA | CMOS Programmable Peripheral Interface |
| 8406602QA | CMOS Programmable Peripheral Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 83C800-009 | 制造商:DRS 功能描述: |
| 83C825EQFP | 制造商:SMSC 功能描述: |
| 83C845 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Microcontrollers for TV and video MTV |
| 83C851 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller with on-chip EEPROM |
| 83C852DIE | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。