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參數(shù)資料
| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁(yè)數(shù)： | 10/136頁(yè) |
| 文件大小： | 1996K |
| 代理商： | 83C795 |
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1.0
The SMC 83C795 Ethernet System Controller
implements the IEEE 802.3 protocol for networks
such as Ethernet, Cheapernet, and 10BaseT. It is a
highly integrated device that shrinks the essence of
a LAN adapter card onto a single piece of silicon. It
includes the 802.3 Media Access Control (MAC)
functions, the Physical Layer Interface (PLI) for
10BASE-T media, and a host interface designed for
simple connection to the Industry Standard
Architecture (ISA) PC/AT bus.
GENERAL DESCRIPTION
To create a LAN adapter only the 83C795, a single
buffer RAM, an EEROM chip, and an optional ROM
for BIOS or IPL code storage are required.
Transformers and supporting analog components
complete an adapter design. All necessary control
logic is provided by the 83C795.
The resulting LAN adapter appears to the host as
a block of I/O registers with a block of shared
memory, unless the I/O pipe is used. The base
address for I/O registers is programmable as is the
base address and size of the buffer memory.
This device is similar to the SMC 83C790 LAN
controller with three major differences:
A small memory cache has been added for host
accesses to shared memory.
An I/O pipe mode has been added to access the
buffer memory.
order to comply with the new ISA Plug and Play
specification.
As with the 83C790 chip, there are two basic modes
of operation: normal and ALTEGO. In the normal
mode, the LAN controller operates much like the
83C690 LAN Controller with received frames being
buffered in a ring of contiguous, fixed-size buffers.
When the ALTEGO feature is enabled, the device
switches to a very different mode of operation. The
differences are summarized here and explained in
detail throughout the specification:
1. Linked-list style of buffering instead of ring
buffers.
2. Different register map for LAN controller, ex-
posing new registers for the linked-list buff-
ering.
Figure 1-1 depicts the 83C795’s functionality.
2.0
The basic features of the 83C795 chip are
summarized here:
Memory caching with time-shared access to
buffer RAM.
Compliant with the ISA Plug And Play specification
Software compatible with 83C790 drivers
Direct interface with ISA bus without TTL buffers
I/O-mapped pipe access to buffer RAM
Extended length option for the twisted-pair port
Underrun detection in early receive mode
Staggered address transfers supported
Ring-empty bit supplied to host
Automatic ring-wrapping
PC-98 bus support through addition of a jumper
Buffered 20 MHz clock output available through
addition of a jumper
Support for diskless workstations via Initial
Program Load ROM
Programmable base address and window size
for buffer memory and IPL ROM
Support for paging of buffer memory and IPL
ROM
Programmable I/O base address
Programmable bus width of either 8 or 16 bits
Zero wait state operation
Automatic loading of host interface
configuration and LAN address from external
serial EEPROM
Separate address and data busses to memory
with no external address latches
7 programmable interrupt levels
Clock oscillator
Full 802.3 MAC layer protocol implementation
with extended features
Support for transmission and reception of
frames up to 32K bytes long
Transmit frame start at any location - no word
alignment required
Two modes of frame buffering: 83C690 mode
and descriptor table mode
Loopback modes - internal and external
Full-duplex DMA capability in loopback mode
Built-in AUI serial interface including drivers and
receivers
FEATURES
GENERAL DESCRIPTION
83C795
1
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