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5.1.5
Read/Write Port = 04
HWR - Hardware Support Register
This register is used to control general purpose
outputs and to switch between configuration and
LAN Address registers.
BIT
7
6
5
4
3
2
1
0
HWR READ
RESET
0
0
1
0
0
0
JMP6
0
SWH
—
ETHR
HOST16
—
ISTAT
PNPJMP
GPOE
BIT
7
6
5
4
3
2
1
0
HWR WRITE
RESET
0
0
1
0
0
0
0
0
SWH
—
—
—
NUKE
—
—
GPOE
Bit 7: SWH
, Switch Register Set
This bit selects between the LAN Address registers
and the Board Configuration registers in the register
map where:
SWH = 0 - LAN Address Registers are visible
SWH = 1 - Configuration Registers are visible
Bit 5: ETHER
, MAC Protocol Type
When ETHER = 1, the 802.3 protocol is provided
by this device. The 83C795 supports only 802.3.
Bit 4: HOST16
This bit reports whether the 83C795 believes it is
connected to an 8-bit or 16-bit host. The chip deter-
mines this by looking at the MEMR pin for activity.
Where:
HOST16 = 0 - 8-bit host
HOST16 = 1 - 16-bit host
Bit 3: NUKE
, Restart
This bit is ’OR’ed together with the RESET pin
signal to form the internal RESET for the chip.
Setting this bit has the same effect on the 83C795
as cycling power on the host machine. The chip will
reset to its initial condition and reload from the
EEROM. This bit is cleared when the reset be-
comes effective. The NUKE reset executes for 256
chip-clock cycles to allow the MA bus to float and
the initialization jumpers to achieve their true val-
ues.
Note
Do not try to access this chip during
reset.
Bit 2: ISTAT
, Interrupt Status
ISTAT returns to 1 when Network Interface Control-
ler has an interrupt active.
Bit 1: PNPJMP, Plug and Play Jumper Installed
A read-only bit that returns a 1 if jumper 6 is in-
stalled. If PNPJ MP = 1 and the PNPEN bit (ER-
FAL.0) is set, then Plug and Play hardware is
enabled.
Bit 0: GPOE
, GPX Pin Output Enable
The output is enabled when GPOE = 1.
83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
16