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參數(shù)資料
| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁(yè)數(shù)： | 41/136頁(yè) |
| 文件大小： | 1996K |
| 代理商： | 83C795 |
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Bit 3: TXEE
, Transmit Error Enable
When TXEE = 1, this bit enables Transmit Error as
defined by the TXE bit in the Interrupt Status Reg-
ister. (See the next register, INTSTAT.)
Bit 2: RXEE
, Receive Error Enable
When RXEE = 1, this bit enables Receive Error as
defined by the RXE bit in the Interrupt Status Reg-
ister. (See the next register, INTSTAT.)
Bit 1: PTXE
, Packet Transmitted Enable
When TXEE = 1, this bit enables Packet Transmit-
ted as defined by the PTX bit in the Interrupt Status
Register. (See the next register, INTSTAT.)
Bit 0: PRXE
, Packet Received Enable
When PRXE = 1, this bit enables Packet Received
as defined by the PRXE bit in the Interrupt Status
Register. (See the next register, INTSTAT.)
5.2.14 INTSTAT - Interrupt Status Register
Normal Map Read/Write Port = 0:17
Linked-List Map Read/Write Port = 0:17
The Interrupt Status Register enables the host to
determine the cause of an interrupt and to evaluate
pending or masked interrupts. Masked-out
interrupts are visible in this register although they
will not generate an IRQ to the host. Pending
interrupts can be cleared by writing ’1’ to the
associated bit of this register. The IRQ signal is
active as long as any unmasked interrupt bit
remains set. For more details, see page 80.
BIT
7
6
5
4
3
2
1
0
INTSTAT
RESET
1
0
0
0
0
0
0
0
RST
ERW
CNT
OVW
TXE
RXE
PTX
PRX
Bit 7: RST
, Reset Status
This bit is set by 83C795 when its Transmit and
Receive sections are stopped in response to the
assertion of the RESET pin or the setting of the
CMD.STP bit. The RST bit does not generate an
interrupt.
Bit 6: ERW
, Early Receive Warning
When this bit is set it indicates that the number of
bytes received in the current frame has exceeded
the programmable limit of the ERWCNT register.
Bit 5: CNT
, Counter Overflow
When this bit is set it indicates that the MSB of one
or more network error counters has been set.
Bit 4: OVW
, Overwrite Warning
This bit is set when the receive DMA must abort
frame reception due to a lack of receive buffers.
Bit 3: TXE
, Transmit Error
This bit is set when excessive collisions, out-of-win-
dow collisions, FIFO underrun, or early transmit
address violations prevent transmission of a
packet.
Bit 2: RXE
, Receive Error
This bit is set when a packet is received with one or
more of the following errors:
CRC error (happens when SEP is enabled)
Frame alignment error (happens when SEP is
enabled)
FIFO overrun
Missed packet (monitor mode)
This interrupt will not be posted if a DMA Abort
occurs, a condition indicated by the assertion of an
OVW interrupt. If RXE is previously set, it will not
be changed due to OVW.
Bit 1: PTX
, Packet Transmitted
This bit is set when a packet is transmitted success-
fully. When the bit ENH.EOTINT is set in Multiple
Packet Transmit mode (see page 5-26), setting of
this interrupt is deferred until the entire transmit
chain has been processed. PTX is then set if any
packet in the chain was transmitted successfully, or
if a zero length transmit chain was processed.
Bit 0: PRX
, Packet Received
When PRX = 1, it indicates that a packet was
received with no errors.
83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
28
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