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參數(shù)資料
| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁(yè)數(shù)： | 58/136頁(yè) |
| 文件大小： | 1996K |
| 代理商： | 83C795 |
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6.1.1
The Zero Wait State signal tells the microprocessor
that it can complete the present bus cycle without
inserting any additional wait cycles. For 16-bit
memory access, this means zero wait states are
inserted by the host bus logic and the access cycle
completes in 2 bus clocks. When asserted for an 8
bit memory access, an ISA bus automatically
inserts the minimum of 2 wait states.
Zero Wait State Response to Host
The response algorithm for the ZWS line depends
upon the memory width, the host access type and
whether the board has been enabled to act as a
16-bit device. The appropriate ZWS response logic
is selected on the basis of the BPR.M16EN control
bit and whether the board is in an 8- or 16-bit slot.
The memory cache can accommodate zero wait
state timing if the following conditions are met:
1. The type of host access matches the current
mode of the cache,
2. The host address matches the value in the
host counter, and
3. The cache either contains at least one valid
data word for reads or has room for at least
one more word for writes.
For writes, zero wait states are also always possible
if the cache is in read mode, or if it is currently
empty.
There is a Zero Wait Enable bit in one of the host
interface registers (CR.ZWSEN) which can be used
to prevent the 83C795 from asserting the Zero Wait
State signal.
6.1.2
Staggered address transfers occur when the host
attempts 16-bit data transfers from system memory
to the local buffer RAM and finds that the address
of the system data differs from the local address in
the least significant bit (one is even, one is odd). In
consequence, the ISA bus forbids 16-bit accesses
to odd locations and breaks the transfer into two
8-bit cycles which run considerably slower.
Staggered Address Transfers
To overcome this on the 795:
FIGURE 6-1. MEMORY CACHE ARRANGEMENT
HOST INTERFACE SECTION
83C795
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