參數(shù)資料
型號： 83C795
廠商： SMSC Corporation
英文描述： Ethernet System Controller
中文描述： 以太網(wǎng)系統(tǒng)控制器
文件頁數(shù)： 78/136頁
文件大小： 1996K
代理商： 83C795
7.0
The LAN Controller consists of 3 basic blocks:
DMA controller, transmitter, and receiver. Each of
these blocks consists of sub-sections. The DMA
controller includes a memory interface unit, control
registers, and a micro-coded sequencer that
handles data buffering for the transmitter and
receiver sections.
LAN CONTROLLER OVERVIEW
The transmitter block has a MAC (Media Access
Control) section that performs the IEEE 802.3
transmission protocol and a Physical Layer
Interface (PLI) section that does Manchester
encoding and drives the cables.
The receiver block has a MAC section that performs
the 802.3 reception protocol and a PLI section that
converts line level differential signals to internal
logic signals while doing clock recovery, and
manchester decoding.
7.1
The DMA controller handles data movement
between the FIFOs and buffer memory for
transmission and reception of frames. All DMA data
traffic is 8-bit wide. One DMA controller is shared
between the transmit and receive functions. The
controller groups memory transfers into bursts of 8
bytes for both transmit and receive functions. The
DMA controller always accesses memory by doing
two single-byte transfers in a row. The burst size
and its trigger levels are shown in Table 7-1.
DMA CONTROLLER
BURST
TRIGGER LEVEL
RX TX
8 bytes
R
≥
8
T
≤
8
TABLE 7-1. DMA BURST LENGTH FIELD
Though internally 8 bits wide, the DMA controller
generates 16-bit addresses. It accesses memory in
2 cycles of the chip’s master clock (per byte).
When conducting a loop-back test, this controller
can handle full-duplex buffering of full length frames
at serial data rates up to 10 Mbps. It does not handle
the general case of independent (concurrent)
transmit and reception processes.
7.1.1
These latches are used to match up the internal
8-bit data path with the external data bus. Assembly
latches build a 16-bit word out of two 8-bit words or
supplies the consecutive bytes when interfacing to
an 8-bit bus. Disassembly latches perform the
inverse function. These are used during DMA
operations and are bypassed when the chip’s
registers are written or read.
Assembly and Disassembly Latches
7.1.2
The memory interface unit (MIU) transfers data
from buffer memory to the internal disassembly
latches and from the internal assembly latches to
buffer memory. It is a part of the DMA controller.
This block generates the memory strobes
(RAMOE, RAMWR) when the DMA is accessing
the buffer RAM.
Memory Interface Unit
MIU operation is initiated by the DMA controller
after it sets up the address for the transfer and puts
outgoing data (receiver functions) into the
assembly latches. The MIU then performs the
memory transfer in the next time slot assigned to
the DMA.
The basic DMA cycles are in Figure 7-1. Real
details can be found in the AC timing section.
LAN CONTROLLER OVERVIEW
83C795
65
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