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參數(shù)資料
| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 85/136頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
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7.4.7.1
During the reception of a frame with early receive
enabled, it is possible for the host to read frame data
from the buffer RAM before the DMA writes it if the
early receive threshold is set too low. The failure
detection logic enables the host to detect if this has
happened; if so, it goes back and recopies the
correct data.
Early Receive Failure Detection
The logic required for this is similar to the logic used
for early transmit underrun detection. The local
memory address is latched every time the DMA
writes to the buffer RAM. When the memory cache
or I/O pipe reads data from the RAM, the local
memory address is compared to the last latched
address. (The least significant 2 bits are not
compared so the detection mechanism has a
granularity of 4 bytes). This comparison is turned
off when the DMA finishes placing the frame in
shared memory. If the two addresses are equal,
ERFBIT (UBRCV.1) is set and the latched address
is stored in the ERFA registers (ERFAL and
ERFAH). When the host reads that ERFBIT is set,
it should begin recopying data from a point at or
before ERFA and reset ERFBIT.
Note
The value in ERFA contains the local
memory address where the failure oc-
curred, not the host address.
The ERFA registers remain set until the host clears
the ERFBIT. For more on ERFBIT, see page 40. For
more on the ERFA registers, see page 22.
7.4.8
The Receive Protocol FSM controls reception of
frames, checks for errors, and posts status to a
register after completion of each reception. It
operates counters for the number of bytes in the
frame and for three types of error conditions. The
receiver protocol FSM can be configured via a
register, allowing some flexibility as to which frames
are to be received.
Receive Protocol FSM
The received byte counter is 16-bits wide. The three
error counters are each 8-bits wide. These will
count from zero up to 255, where they stick to avoid
wrap-around. The error counters are self-clearing
when read and they can generate a shared interrupt
condition when any of them have counted up to 192.
The Receive Protocol FSM interfaces with the DMA
section to coordinate buffering of received frames.
It informs the DMA of abort conditions, should they
occur as well as valid completions of received
frames. After the frame has been buffered to
memory by the DMA, the DMA section copies the
Receiver Status Register (RSTAT) and the number
of bytes received from the receiver into the header
of the buffer.
The receiver FIFO is monitored for overflow
conditions and if one occurs, frame reception is
terminated and an error flag is posted to the Status
Register.
The Receiver section is enabled by setting the Start
and clearing the Stop bits in the Command Register
- CMD.STA and CMD.STP. Until enabled, the
receiver section ignores incoming frames. Once the
Start bit has been set, it remains true internally until
the Stop bit is set or the chip is reset. Clearing the
Start bit in Command Register does not cause the
receiver section to stop operating.
If the Stop bit is set while receiver is operational, it
will complete the handling of any ongoing frame and
then go to a soft reset condition, ignoring new
incoming frames. The receiver will clear the RSTAT
Register when the current frame is finished and
posted. When both transmitter and receiver
sections are stopped, the RST bit in the interrupt
status register will be set. It should be noted that the
DMA controller may remain active while Stop is set.
The protocol machine can be configured to operate
in a "Monitor Mode" which checks validity of
incoming frames and maintains error statistics for
them but does not store them in memory. Each time
an acceptable frame is completed while in this
mode, the Missed Packet Counter (MPCNT) is
incremented. This counter is not incremented by
FIFO overflows.
7.4.9
IEEE 802.3 packets consist of these fields and are
therefore processed in this order:
Preamble field
SFD field
DA field
SA field
Reception Process
83C795
LAN CONTROLLER OVERVIEW
72
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