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5.2.35 TBEGIN - Transmit Buffer Starting
Address Register
Linked-List Map Read Port = 2:13
Linked-List Map Write Port = 0:15
This register holds the upper 8 bits of the starting
address of the transmit buffer descriptor table. The
lower 8 bits are assumed to be zero. Refer to page
80 for more information.
BIT
7
6
5
4
3
2
1
0
TBEGIN
RESET
X
X
X
X
X
X
X
X
TB15
TB14
TB13
TB12
TB11
TB10
TB09
TB08
5.2.36 TCNTH - Transmit Frame Length High
Register
Normal Map Read Port = 2:16 Normal Map Write
Port = 0:16
This register contains the upper 8 bits of a
two-register set that holds the byte count for the
frame to be transmitted. This byte count must
include the DA, SA, and data fields. If CRC
generation is inhibited, this count must also include
the CRC field in the buffer.
BIT
7
6
5
4
3
2
1
0
TCNTH
RESET
X
X
X
X
X
X
X
X
L15
L14
L13
L12
L11
L10
L09
L08
5.2.37 TCNTL - Transmit Frame Length Low
Register
Normal Map Read Port = 2:13 Normal Map Write
Port = 0:15
This register contains the lower 8 bits of a
two-register set that holds the byte count for the
frame to be transmitted. This byte count must
include the DA, SA, and data fields. If CRC
generation is inhibited, this count must also include
the CRC field in the buffer.
BIT
7
6
5
4
3
2
1
0
TCNTL
RESET
X
X
X
X
X
X
X
X
L07
L06
L05
L04
L03
L02
L01
L00
5.2.38 TCON - Transmit Configuration
Register
Normal Map Read Port = 2:1D Normal Map Write
Port = 0:1D
Linked-List Map Read Port = 2:1D Linked-List Map
Write Port = 0:1D
This register controls loopback options and
transmitter mode operations.
BIT
7
6
5
4
3
2
1
0
TCON
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
LB1
LB0
CRCN
Bits 2-1: LB1, LB0
, Loopback Test Selection
These two bits are decoded as shown in Table 5-12.
83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
36