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Bits 3-0: CT3-CT0
, Collision Counter
These bits indicate the value of the collision
counter. They are always readable.
5.2.5
Normal Map Read Port = 0:1E
Linked-List Map Read Port = 0:1E
CRCCNT - CRC Error Counter
This register is incremented by the receive unit
when a packet is received with a CRC error. Only
packets whose address is recognized will be
included in this tally. When a ’runt’ frame is received
with a CRC error, CRCCNT is incremented if
RCON.RUNTS is enabled (see page 32). The
counter will increment to 255 and stick if additional
CRC errors are detected. The counter is cleared
when read.
BIT
7
6
5
4
3
2
1
0
CRCCNT
RESET
0
0
0
0
0
0
0
0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
5.2.6
CURR - Current Frame Buffer Pointer
Register
Normal Map Read/Write Port = 1:17
This register points to the first buffer used for
storage of the present frame. It is used by DMA as
a backup address for recovering buffers in case of
a flawed packet and facilitates storage of buffer
header information. The CURR register should be
initialized to the same value as RSTART (see page
33) and not altered thereafter by the user unless the
controller is reset. Only A08-A15 are specified
since all buffers are aligned on 256-byte
boundaries.
BIT
7
6
5
4
3
2
1
0
CURR
RESET
X
X
X
X
X
X
X
X
A15
A14
A13
A12
A11
A10
A09
A08
5.2.7
CURRH - Current Frame Buffer
Descriptor Pointer Register High
Linked-List Map Read/Write Port = 1:17
This register is one of a pair of registers (CURRH
and CURRL) that point to the first buffer descriptor
used for storage of the present frame. They are
used by DMA as a backup address for recovering
buffers in the case of a flawed packet and to
facilitate storage of buffer header information.
Neither the CURRH nor CURRL registers should
be altered by the user. They are accessible for test
purposes only.
BIT
7
6
5
4
3
2
1
0
CURRH
RESET
X
X
X
X
X
X
X
X
A15
A14
A13
A12
A11
A10
A09
A08
5.2.8
CURRL - Current Frame Buffer
Descriptor Pointer Register Low
Linked-List Map Read/Write Port = 0:13
This register is one of a pair of registers (CURRH
and CURRL) that point to the first buffer descriptor
used for storage of the present frame. They are
used by DMA as a backup address for recovering
buffers in the case of a flawed packet and to
facilitate storage of buffer header information.
Neither the CURRH nor CURRL registers should
be altered by the user. They are accessible for test
purposes only.
ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
25