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參數(shù)資料
| 型號： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 91/136頁 |
| 文件大小： | 1996K |
| 代理商： | 83C795 |
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Once the DMA has filled the Transmit FIFO with the
last byte of the packet, it sets a flag. When the FIFO
becomes empty, it signifies the end of the frame.
CRC computation stops and the CRC is appended
serially to the frame, most significant bit first.
7.6.7.3
If the FIFO becomes empty before the internal flag
is set, it is considered a transmit underflow and is
posted as a transmit error in the Transmit Status
(TSTAT) Register. In this case, transmission of the
packet is aborted and an interrupt can be
generated.
Transmit Underrun
7.6.7.4
This feature is used to facilitate initiation of
transmission prior to completion of assembly of the
outgoing frame in the transmit buffer.
Early Transmit Underrun Protection
Early transmit underrun protection is controlled by
two bits in the Command Register - CMD.DISETCH
and CMD.ENETCH. Setting DISETCH to ’1’
disables early transmit underrun checking and
setting ENETCH to ’1’ enables checking. Writing
both bits to zero leaves transmit checking in its
previous state. Setting both bits to ’1’ is illegal. This
operation works the same as the Command
Register start and stop bits for bringing the chip on
and offline.
While early transmit underrun checking is enabled,
the memory address is latched each time the host
does a write to the buffer memory (the actual
memory address is used, not the host address).
When the DMA reads packet data from the buffer
memory, the memory address is compared to the
most recently-latched memory write address
(written from the host with ETCHON only). The
DMA distinguishes between accesses to descriptor
table entries and actual packet data.
If early transmit checking is on, and the DMA’s
memory read address is greater than the absolute
value of the latched memory write address, a
"buffer underrun" condition is set. This condition
aborts the transmitter which in turn aborts the DMA.
The condition is cleared when the DMA detects the
abort and clears the transmit FIFO. The transmit
abort is reported as though it were a FIFO underrun
and both the TSTAT.UNDER and INTSTAT.RXE
flag bits are set.
7.6.7.5
When a collision is reported on the CD pin, the
transmitter sends a 32-bit sequence composed of
all ’1’ bits as a jam signal, then terminates its
transmission. If collision occurs during the
preamble of a frame, the remainder of the preamble
is sent before sending the jam signal.
Collisions
If the collision occurred after the end of one slot
time, transmission is aborted without retry after
sending a jam pattern. This is considered an
out-of-window collision and posts a status bit in the
TSTAT register (TSTAT.OWC) and is a contributor
to the TXE flag in the INTSTAT Register.
For collisions that occur within the first slot time of
a frame, a counter of retries is incremented and
checked against the retry limit (16). If the number
of retries is less than the limit, a back-off delay (in
units of slot-time) is chosen at random. The
transmitter then requests the frame’s
retransmission from memory and delay is initiated.
The DMA controller clears out the transmit FIFO,
loads its pointer to the start of frame in memory, and
waits for the abort signal to subside. The FIFO is
loaded in the same manner as it was initially. If the
maximum number of collisions (16) is exceeded,
transmission is aborted without further retries and
no back-off delay is executed.
83C795
LAN CONTROLLER OVERVIEW
78
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