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參數(shù)資料
| 型號： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 50/136頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
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LB1 LB0
0
0
Operation
0
1
Normal (no loopback)
Internal loopback (before MAN
CODEC)
Internal loopback, LOOP pin is high
(after MAN CODEC)
External loopback with LOOP pin low
1
0
1
1
TABLE 5-12. LOOPBACK TEST SELECTION
Bit 0: CRCN
, CRC Generation Inhibition
Setting this bit inhibits generation of CRC during
transmission of frame. The user is responsible for
calculating the frame’s CRC and placing it in the
buffer in such a way that when the last 4 bytes of
the buffer are shifted out, they form the correct CRC
for the frame. Note that the serializer shifts bytes
out LSB first whereas the CRC must be shifted MSB
first. The operation of the receiver is not affected by
this bit.
5.2.39 TDOWNH - Transfer Count High
Register
Linked-List Map Read/Write Port = 2:1B
This register contains the upper 8 bits for the
register pair used by the DMA controller as a
scratch pad for the bytes remaining to transfer
count during the transmission process. They can
be accessed for manufacturing test purposes.
Note
Writing to these registers while commu-
nication is taking place may cause er-
rors in the DMA process.
BIT
7
6
5
4
3
2
1
0
TDOWNH
RESET
X
X
X
X
X
X
X
X
A15
A14
A13
A12
A11
A10
A09
A08
5.2.40 TDOWNL - Transfer Count Low
Register
Linked-List Map Read/Write Port = 2:1A
This register contains the lower 8 bits for the
register pair used by the DMA controller as a
scratch pad for the bytes remaining to transfer
count during the transmission process. They can
be accessed for manufacturing test purposes.
Note
Writing to these registers while commu-
nication is taking place may cause er-
rors in the DMA process.
BIT
7
6
5
4
3
2
1
0
TDOWNL
RESET
X
X
X
X
X
X
X
X
A07
A06
A05
A04
A03
A02
A01
A00
5.2.41 TEND - Transfer Buffer End Register
Linked-List Map Read Port = 2:14
Linked-List Map Write Port = 0:14
This register holds the upper 8 bits of the first
address beyond the end of the transmit buffer
descriptor table. The lower 8 bits are assumed to
be zero. The table lies between (TBEGIN *256)
and (TEND *256 - 1). Refer to page 80 for more
information.
BIT
7
6
5
4
3
2
1
0
TEND
RESET
X
X
X
X
X
X
X
X
TE15
TE14
TE13
TE12
TE11
TE10
TE9
TE8
ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
37
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