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參數(shù)資料
| 型號： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 86/136頁 |
| 文件大小： | 1996K |
| 代理商： | 83C795 |
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Data field
CRC field
Each of these fields is explained in the following
sections.
7.4.9.1
The preamble field is used to train the Manchester
decoder and to detect carrier. If carrier is detected,
preamble passes through the receive deserializer
which discards it while searching for the
S tart-of-Frame Delimiter (SFD) symbol. On
detecting a good SFD, a VALID_FRAME signal is
asserted and the receive FIFO is cleared to accept
the received frame. The receive FIFO is loaded by
the deserializer with octets (bytes) starting with the
first bit after SFD.
Start of Frame
While the destination address (DA field) is being
checked for recognition, the receive DMA is
disabled. If the address is recognized, the DMA is
enabled and transfer to memory begins when the
FIFO fills to the programmed burst level. If the
frame’s address is not recognized, the receive unit
clears out the FIFO, stops filling it, and waits for the
start of the next frame.
The source address and data fields are passed to
buffer memory. In some protocols, the first 2 bytes
of the data field denote a frame length. These bytes
are not interpreted by the SMC795. They are
treated as ordinary data.
7.4.9.2
If there is a loss of carrier sense, 3 dribble clocks
(receive clocks that occur after the loss of carrier
sense) are needed to ensure the synchronizations
of all line signals to the receiver circuits. When using
the internal Manchester decoder (either 10BASE-T
or AUI interfaces), this decoder automatically
supplies sufficient dribble clocks to the receiver to
complete processing of the frame. When the
Manchester decoder is bypassed, it is necessary to
supply dribble clocks at the XRXC pin after XCRS
terminates.
End of Frame
The CRC from the received frame is sent to
memory with the frame via DMA and is included in
the byte count posted in the buffer header.
If the receive unit detects errors in the frame (such
as an incorrect CRC, an alignment problem, a
foreshortened frame), it can abort reception
depending on the configuration of the Save Errored
Packets and Accept Runt Frames bits of the
Receive Configuration Register - RCON.SEP and
RCON.RUNTS respectively. Certain other types of
errors (including FIFO overflow and Receiver Buffer
Overwrite) always abort reception.
If reception is aborted, the DMA controller stops
sending bytes to the buffer, the Receive Status
Register (RSR) and the Interrupt Status Register
(ISR) are updated, and the receive unit waits for the
next frame to begin.
No buffer header will be posted for the frames that
have not been accepted; the previous contents of
the header location will remain unchanged.
The received packet length should be less than
32,764 bytes, including DA, SA, data, and CRC.
The receiver does not reject longer frames but it
may be hard to fit the contents into available buffer
space. The buffer ring must always have enough
space to contain the entire frame with a 4-byte
header. Packets larger than the available buffer
space will not be received, regardless of the SEP
bit in the RCON Register. Such frames will be
posted as ring overwrites and causes the OVW
interrupt to be set.
Receiver interrupts (RXE for frames with errors and
PRX for frames without errors) indicate the DMA
has completely posted the frame to memory. If the
DMA aborts, these interrupts are not set for the
current frame. If set previously, they remain
unchanged. Packets shorter than 64 bytes will be
received only when the Accept Runts bit
(RCON.RUNTS) is enabled.
7.4.10 Receiver Blinding
The Receiver Carrier Sense function is blinded for
a period of 4.0
μ
sec starting at the end of (XCRS +
XCOL) when the device has transmitted a frame.
This allows the heartbeat to be detected without
resetting the deference timer and ensures that an
improperly-spaced frame will not interfere with
proper posting of status for a new reception.
LAN CONTROLLER OVERVIEW
83C795
73
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