參數(shù)資料
型號： 83C795
廠商： SMSC Corporation
英文描述： Ethernet System Controller
中文描述： 以太網(wǎng)系統(tǒng)控制器
文件頁數(shù)： 59/136頁
文件大?。?/td> 1996K
代理商： 83C795
1. Make sure the system address is even. If the
address comes out odd, transfer one byte.
2. Set the STAG bit (ICR.6). This forces a ’1’ into
bit 0 of the Buffer Counter when the address
is loaded
NOTE
This only happens on a cache miss.
This makes it possible for the host to perform an
even-to-even transfer, but the internal address to
the local RAM is transformed to an odd address.
6.1.3
Do not use this chip for micro-channel applications.
A future variant may be created with the necessary
interface logic.
Operation on Micro-Channel Adapters
6.2
The I/O-mapped pipe provides another method for
accessing the local buffer RAM. When enabled, all
memory accesses take place through two I/O
registers in the host interface I/O space (IOPL and
IOPH). The data in these two I/O locations
corresponds to the the location in the buffer
memory indicated by the Buffer Counter. When run
in this mode, the memory-space address decoders
are disabled, so the adapter will not use any host
memory space for the buffer RAM.
I/O-MAPPED PIPE
The mechanism used by the I/O-pipe is similar to
that used by the memory cache except for address
handling. In this method, the address is loaded into
the Buffer Counter by performing two consecutive
writes to the IOPA register. The first write stores the
lower half of the address into a temporary register.
The second write stores data directly into the upper
half of the buffer counter and moves the temporary
register into the lower half. Any access to the chip
between the two writes will cause the state machine
to not load the address. The Host Counter is not
used during this process.
To use the I/O-pipe, the IOPEN bit (ICR.4) must be
set to 1, and the MENB bit (CR.6) must be set to 0.
All 8-bit transfers must take place through IOPL
only. Also, it is imperative that when switching from
Read Mode to Write Mode, the address must be
reloaded even if the counter holds the correct value.
6.3
Three address decoders are used to detect host
accesses to the buffer memory, I/O registers, and
IPL ROM. These decoders observe the SA19-SA05
lines to decode access within a range of addresses
(a window). The buffer and IPL ROM decoders
allow placement of their respective windows on any
8K boundary between C0000H and EFFFFH
regardless of window size. This allows windows to
start on even or odd 8K boundaries. The RAM and
IPL ROM are scrollable (and therefore can be
paged) through their programmable window size as
shown in Table 6-1 below.
ADDRESS DECODERS
DECODER
MIN
BASE
MAX
BASE
INCREMENT
WINDOW
SIZES
BUFFER
C0000H
EE000H
2000H
8K
16K
32K
64K*
DISABLED
8K
16K
32K
DISABLED
32 Bytes
IPL ROM
C0000H
EE000H
2000H
I/O BASE
0200H
E3E0H
20H, 2000H
TABLE 6-1. HOST INTERFACE ADDRESS DECODERS
* Plug and Play cannot utilize this window size.
83C795
HOST INTERFACE SECTION
46
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