參數(shù)資料
型號(hào)： 28F640C3
廠商： Intel Corp.
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 3伏高級(jí)啟動(dòng)塊閃存（3伏高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 40/70頁(yè)
文件大小： 894K
代理商： 28F640C3
28F800C3, 28F160C3, 28F320C3, 28F640C3
34
3UHOLPLQDU\
AC Characteristics—Write Operations, continued
NOTES:
1. Write pulse width (t
) is defined from CE# or WE# going low (whichever goes low last)
to CE# or WE# going
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, write pulse width
high (t
) is defined from CE# or WE# going high (whichever goes high first)
to CE# or WE# going low
(whichever goes low first). Hence, t
= t
= t
= t
= t
EHWL
.
2. Refer to
Table 5, “Command Bus Operations” on page 13
for valid A
IN
IN
.
3. Sampled, but not 100% tested.
Write timing characteristics during erase suspend are the same as during write-only operations.
See
Figure 6, “Input/Output Reference Waveform” on page 27
for timing measurements and maximum
allowable input slew rate.
See
Figure 8, “AC Waveform: Read Operations” on page 32
.
4. V
CC
Max = 3.3 V for 32-Mbit and 64-Mbit densities.
#
Sym
Parameter
Density
16 Mbit
Unit
Product
70 ns
80 ns
90 ns
110 ns
3.0 V – 3.6 V
80
100
2.7 V – 3.6 V
70
80
90
110
Note
Min
Min
Min
Min
Min
Min
W1
t
PHWL
/
t
PHEL
RP# High Recovery to WE#
(CE#) Going Low
150
150
150
150
150
150
ns
W2
t
ELWL
/
t
WLEL
CE# (WE#) Setup to WE#
(CE#) Going Low
0
0
0
0
0
0
ns
W3
t
WLWH
/
t
ELEH
WE# (CE#) Pulse Width
1
45
50
50
60
70
70
ns
W4
t
DVWH
/
t
DVEH
Data Setup to WE# (CE#)
Going High
2
40
40
50
50
60
60
ns
W5
t
AVWH
/
t
AVEH
Address Setup to WE# (CE#)
Going High
2
50
50
50
60
70
70
ns
W6
t
WHEH
/
t
EHWH
CE# (WE#) Hold Time from
WE# (CE#) High
0
0
0
0
0
0
ns
W7
t
WHDX
/
t
EHDX
Data Hold Time from WE#
(CE#) High
2
0
0
0
0
0
0
ns
W8
t
WHAX
/
t
EHAX
Address Hold Time from WE#
(CE#) High
2
0
0
0
0
0
0
ns
W9
t
WHWL /
t
EHEL
WE# (CE#) Pulse Width High
1
25
30
30
30
30
30
ns
W10
t
VPWH
/
t
VPEH
V
Setup to WE# (CE#)
Going High
3
200
200
200
200
200
200
ns
W11
t
QVVL
V
PP
Hold from Valid SRD
3
0
0
0
0
0
0
ns
W12
t
BHWH
/
t
BHEH
WP# Setup to WE# (CE#)
Going High
3
0
0
0
0
0
0
ns
W13
t
QVBL
WP#
Hold from Valid SRD
3
0
0
0
0
0
0
ns
W14
t
WHGL
WE# High to OE# Going Low
3
30
30
30
30
30
30
ns
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