參數(shù)資料
型號(hào)： 28F640C3
廠商： Intel Corp.
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 3伏高級(jí)啟動(dòng)塊閃存（3伏高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 20/70頁(yè)
文件大?。?/td> 894K
代理商： 28F640C3
28F800C3, 28F160C3, 28F320C3, 28F640C3
14
3UHOLPLQDU\
NOTE:
See
Appendix A
for mode transition information.
Table 6. Command Codes and Descriptions
Code
Device Mode
Description
FF
Read Array
This command places the device in read array mode which outputs array data on the data pins.
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See
Section 3.2.5
.
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”
(b) place the device into the read status register mode, and (c) wait for another command. See
Section 3.2.6
.
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches and begin erasing the block indicated on the address pins. During program/
erase, the device will respond only to the Read Status Register, Program Suspend and Erase
Suspend commands and will output status register data when CE# or OE# is toggled.
If a program or erase operation was previously suspended, this command will resume that
operation.
If the previous command was Configuration Set-Up, the CUI will latch the address and unlock
the block indicated on the address pins. If the block had been previously set to Lock-Down, this
operation will have no effect. (
Section 3.3
)
Issuing this command will begin to suspend the currently executing program/erase operation.
The status register will indicate when the operation has been successfully suspended by
setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit
(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip if RP# is driven to V
IL
. See Sections 3.2.5.1 and 3.2.6.1.
This command places the device into read status register mode. Reading the device will output
the contents of the status register, regardless of the address presented to the device. The
device automatically enters this mode after a program or erase operation has been initiated.
See
Section 3.2.3
.
The WSM can set the block lock status (SR.1) , V
PP
Status (SR.3), program status (SR.4), and
erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
Puts the device into the read configuration mode so that reading the device will output the
manufacturer/device codes or block lock status.
Section 3.2.2
.
Prepares the CUI for changes to the device configuration, such as block locking changes. If the
next command is not Block Unlock, Block Lock, or Block Lock-Down, then the CUI will set both
the program and erase status register bits to indicate a command sequence error. See
Section
3.2
.
If the previous command was Configuration Set-Up, the CUI will latch the address and lock the
block indicated on the address pins. (
Section 3.3
)
If the previous command was a Configuration Set-Up command, the CUI will latch the address
and lock-down the block indicated on the address pins. (
Section 3.3
)
Puts the device into the read query mode so that reading the device will output Common Flash
Interface information. See
Section 3.2.4
and
Appendix C
.
This is a two-cycle command. The first cycle prepares the CUI for a program operation to the
protection register. The second cycle latches addresses and data information and initiates the
WSM to execute the Protection Program algorithm to the protection register. The flash outputs
status register data when CE# or OE# is toggled. A Read Array command is required after
programming to read array data. See
Section 3.4
.
Operates the same as Program Set
-
up command. (See 40H/Program Set-Up)
Unassigned commands that should not be used. Intel reserves the right to redefine these
codes for future functions.
40
Program Set-Up
20
Erase Set-Up
D0
Erase Confirm
Program/Erase
Resume
Unlock Block
B0
Program
Suspend
Erase
Suspend
70
Read Status
Register
50
Clear Status
Register
90
Read
Configuration
60
Configuration
Set-Up
01
Lock-Block
2F
Lock-Down
98
Read
Query
C0
Protection
Program
Setup
10
Alt. Prog Set-Up
Invalid/
Reserved
00
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