參數資料
型號: 28F640C3
廠商: Intel Corp.
英文描述: 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導塊閃速存儲器)
中文描述: 3伏高級啟動塊閃存(3伏高級快速引導塊閃速存儲器)
文件頁數: 17/70頁
文件大?。?/td> 894K
代理商: 28F640C3
28F800C3, 28F160C3, 28F320C3, 28F640C3
3UHOLPLQDU\
11
before reading the status register to determine if an error occurred during that series. Clear the
status register before beginning another command or sequence. Note that this is different from a
burst device. The Read Array command must be issued before data can be read from the memory
array. Resetting the device also clears the status register.
3.2.4
Read Query
The read query mode outputs Common Flash Interface (CFI) data when the device is read. This can
be accessed by writing the Read Query Command (98H). The CFI data structure contains
information such as block size, density, command set and electrical specifications. Once in this
mode, read cycles from addresses shown in
Appendix C
retrieve the specified information. To
return to read array mode, write the Read Array command (FFH).
3.2.5
Program Mode
Programming is executed using a two
-
write sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program desired bits
of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If the user
attempts to program “1”s, the memory cell contents do not change and no error occurs.
The status register indicates programming status: while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If
SR.3 is set then V
PP
was not within acceptable limits, and the WSM did not execute the program
command. If SR.1 is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status register reads, be
sure to reset the CUI to read array mode.
3.2.5.1
Suspending and Resuming Program
The Program Suspend command halts an in
-
progress program operation so that data can be read
from other locations of memory. Once the programming process starts, writing the Program
Suspend command to the CUI requests that the WSM suspend the program sequence (at
predetermined points in the program algorithm). The device continues to output status register data
after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will
determine when the program operation has been suspended (both will be set to “1”). t
WHRH1
/
t
EHRH1
specify the program suspend latency.
A Read Array command can now be written to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended are Read Status
Register, Read Configuration, Read Query, and Program Resume. After the Program Resume
command is written to the flash memory, the WSM will continue with the programming process
and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically
outputs status register data when read (see
Figure 12, “Program Suspend/Resume Flowchart” on
page 45
) after the Program Resume command is written. V
PP
must remain at the same V
PP
level
used for program while in program suspend mode. RP# must also remain at V
IH
.
相關PDF資料
PDF描述
28F640J3C-120 Intel StrataFlash Memory (J3)
28LV64A 64K (8K x 8) Low Voltage CMOS EEPROM(低壓,64K位, CMOS 并行EEPROM)
28M0U 60V 300mA MONOLITHIC DIODE ARRAY
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