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參數(shù)資料
| 型號： | 28F640C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器) |
| 中文描述： | 3伏高級啟動(dòng)塊閃存（3伏高級快速引導(dǎo)塊閃速存儲器） |
| 文件頁數(shù)： | 27/70頁 |
| 文件大?。?/td> | 894K |
| 代理商： | 28F640C3 |
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28F800C3, 28F160C3, 28F320C3, 28F640C3
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21
3.6.2
Automatic Power Savings (APS)
Automatic Power Savings provides low
-
power operation during read mode. After data is read from
the memory array and the address lines are quiescent, APS circuitry places the device in a mode
where typical current is comparable to I
CCS
. The flash stays in this static state with outputs valid
until a new location is read.
3.6.3
Standby Power
When CE# is at a logic
-
high level (V
IH
) and the device is in read mode, the flash memory is in
standby mode, which disables much of the device’s circuitry and substantially reduces power
consumption. Outputs are placed in a high
-
impedance state independent of the status of the OE#
signal. If CE# transitions to a logic
-
high level during erase or program operations, the device will
continue to perform the operation and consume corresponding active power until the operation is
completed.
System engineers should analyze the breakdown of standby time versus active time and quantify
the respective power consumption in each mode for their specific application. This will provide a
more accurate measure of application
-
specific power and energy requirements.
3.6.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = V
IL
(GND
±
0.2 V). During read modes,
RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery
from deep power-down requires a minimum time of t
PHQV
for read operations and t
PHWL
/t
PHEL
for
write operations.
During program or erase modes, RP# transitioning low will abort the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low power savings mode (RP# transitioning to V
IL
or turning off power to
the device clears the status register).
3.7
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required, since
the device is indifferent as to which power supply,
V
PP
or V
CC
, powers-up first.
3.7.1
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
CC
voltages are above V
LKO
. Since
both WE# and CE# must be low for a command write, driving either signal to V
IH
will
inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to V
IH
, regardless of the state of its control inputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F640J3C-120 | Intel StrataFlash Memory (J3) |
| 28LV64A | 64K (8K x 8) Low Voltage CMOS EEPROM(低壓,64K位, CMOS 并行EEPROM) |
| 28M0U | 60V 300mA MONOLITHIC DIODE ARRAY |
| 28M0DC | 60V 300mA MONOLITHIC DIODE ARRAY |
| 28M0DS | 60V 300mA MONOLITHIC DIODE ARRAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640C3BC80 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J3C120 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J3C-120 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J3D75 | 制造商:Intel 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J5 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory |
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