參數(shù)資料
型號(hào)： 28F640C3
廠商： Intel Corp.
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 3伏高級(jí)啟動(dòng)塊閃存（3伏高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 15/70頁(yè)
文件大?。?/td> 894K
代理商： 28F640C3
28F800C3, 28F160C3, 28F320C3, 28F640C3
3UHOLPLQDU\
9
Similar to any automated device, it is important to assert RP# during system reset. When the
system comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or block erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel
Flash memories
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1.5
Write
A write takes place when both CE# and WE# are low and OE# is high. Commands are written to
the Command User Interface (CUI) using standard microprocessor write timings to control flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. See
Figure
9, “AC Waveform: Program and Erase Operations” on page 38
. The available commands are
shown in
Table 6 on page 14
, and
Appendix A
provides detailed information on moving between
the different modes of operation using CUI commands.
There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User Interface (CUI) initiates a sequence of internally
-
timed functions that culminate in the completion of the requested task (unless that operation is
aborted by either RP# being driven to V
IL
for t
PLRH
or an appropriate suspend command).
3.2
Modes of Operation
The flash memory has four read modes and two write modes. The read modes are read array, read
configuration, read status, and read query. The write modes are program and erase. Three
additional modes (erase suspend to program, erase suspend to read and program suspend to read)
are available only during suspended operations. These modes are reached using the commands
summarized in Tables 5 and 6. For a comprehensive chart showing the state transitions, see
Appendix A
.
3.2.1
Read Array
When RP# transitions from V
IL
(reset) to V
IH
, the device defaults to read array mode and will
respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
When the device is in read array mode, four control signals control data output:
WE# must be logic high (V
IH
)
CE# must be logic low (V
IL
)
OE# must be logic low (V
IL
)
RP# must be logic high (V
IH
)
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read array mode, as would be the case after a program or erase operation, the Read Array
command (FFH) must be written to the CUI before array reads can take place.
相關(guān)PDF資料
PDF描述
28F640J3C-120 Intel StrataFlash Memory (J3)
28LV64A 64K (8K x 8) Low Voltage CMOS EEPROM(低壓,64K位, CMOS 并行EEPROM)
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28M0DC 60V 300mA MONOLITHIC DIODE ARRAY
28M0DS 60V 300mA MONOLITHIC DIODE ARRAY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F640C3BC80 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3C120 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3C-120 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3D75 制造商:Intel 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J5 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory
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