- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372961 > Z85233 (ZiLOG, Inc.) The Zilog SCC Serial Communication Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 96/317頁 |
| 文件大小： | 3201K |
| 代理商： | Z85233 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁當(dāng)前第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁第305頁第306頁第307頁第308頁第309頁第310頁第311頁第312頁第313頁第314頁第315頁第316頁第317頁
SCC/ESCC User’s Manual
Data Communication Modes
4-21
4
near the end of the frame to allow the correct transmission
of the CRC.
In this paragraph the term “completely sent” means shifted
out of the Transmit Shift register, not shifted out of the zero
inserter, which is an additional five bit times of delay. In
SDLC mode, if the transmitter is disabled during transmis-
sion of a character, that character will be “completely sent.”
This applies to both data and flags. However, if the trans-
mitter is disabled during the transmission of the CRC, the
16-bit transmission will be completed, but the remaining
bits are from the Flag register rather than the remainder of
the CRC.
The initialization sequence for the transmitter in SDLC
mode is:
1.
WR4 selects the mode.
2.
WR10 modifies it if necessary.
3.
WR7 programs the flag.
4.
WR3 and WR5 selects the various options.
At this point the other registers should be initialized as nec-
essary. When all of this is complete, the transmitter may be
enabled by setting bit D3 of WR5 to 1. Now that the trans-
mitter is enabled, the CRC generator may be initialized by
issuing the Reset Tx CRC Generator command in WR0.
4.4.1.1 Modem Control signals related to SDLC
Transmit
There are two modem control signals associated with the
transmitter provided by the SCC. The /RTS pin is a simple
output that carries the inverted state of the RTS bit (D1) in
WR5. The /CTS pin is ordinarily a simple input to the CTS
bit in RR0. However, if Auto Enables mode is selected, this
pin becomes an enable for the transmitter. If Auto Enables
is on and the /CTS pin is High, the transmitter is disabled.
The transmitter is enabled if the /CTS pin is Low.
4.4.1.2 ESCC Enhancements for SDLC Transmit
The ESCC has the following enhancements available in
the SDLC mode of operation which can reduce CPU over-
head dramatically. These features are:
I
Deeper Transmit FIFO (Four Bytes)
I
CRC takes priority over the data
I
Auto EOM Reset (WR7' bit D1)
I
Auto Tx Flag (WR7' bit D0)
I
Auto RTS Deactivation (WR7' bit D2)
I
TxD pin forced High after closing flag in NRZI mode
Deeper Transmit FIFO:
The ESCC has a four byte deep
Transmit FIFO, where the NMOS/CMOS version has a
one byte deep transmit buffer. To maximize the system’s
performance, there are two modes of operation for the
transmit interrupt and DMA request, which are pro-
grammed by bit D5 of WR7'.
The ESCC sets WR7' bit D5 to 1 following a hardware or
software reset. This is done to provide maximum compat-
ibility with existing SCC designs. In this mode, the ESCC
generates the transmit buffer empty interrupt and DMA
transmit request when the Transmit FIFO is completely
empty. Interrupt driven systems can maximize efficiency
by writing four bytes for each entry into the Transmit Inter-
rupt Service Routine (TISR), filling the Transmit FIFO with-
out having to check any status bits. Since the TBE status
bit is set if the entry location of the FIFO is empty, this bit
can be tested at any time if more data is written. Applica-
tions
requiring
software
NMOS/CMOS version can test the TBE bit in the TISR af-
ter each data write to determine if more data can be writ-
ten. This allows a system with an ESCC to minimize the
number of transmit interrupts, but not overflow SCC sys-
tems. DMA driven systems originally designed for the SCC
can use this mode to reassert the DMA request for more
data after the first byte written to the FIFO is loaded to the
Transmit Shift register. Consequently, any subsequent re-
assertion allows the DMA sufficient time to detect the High-
to-Low edge.
compatibility
with
the
If WR7' D5 is reset to 0, the transmit buffer empty interrupt
and DMA request are generated when the entry location of
the FIFO is empty. Therefore, if more than one byte is re-
quired to fill the entry location of the FIFO, the ESCC gen-
erates interrupts or DMA requests until the entry location
of the FIFO is filled. The transmit DMA request pin (either
/WAIT//REQ or /DTR//REQ) goes inactive after each data
transfer, then goes active again and, consequently, gener-
ates a High-to-Low edge for each byte. Edge triggered
DMA should be enabled before the transmit DMA function
is enabled in the ESCC to guarantee that the ESCC does
not generate the edge before the DMA is ready.
CRC takes priority over data:
On the NMOS/CMOS
version, the data has higher priority over CRC data. Writ-
ing data before the Tx interrupt, after loading the closing
flag into the Transmit Shift register, terminates the packet
illegally. In this case, CRC byte(s) are replaced with Flag
or Sync patterns, followed by the data written. On the ES-
CC, CRC has priority over the data. Consequently, after
the Underrun/EOM (End of message) interrupt occurs,
the ESCC accepts the data for the next packet without
fear of collapsing the packet. On the ESCC, if data was
written during the time period described above, the TBE
bit (bit D2 of RR0) is NOT set; even if the 2nd TxIP is
guaranteed to set when the flag/sync pattern is loaded
into the Transmit Shift register (Section 2.4.8). For the
detailed timing on this, refer to Figures 2-17 and 2-18.
UM010901-0601
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Z8602 | CAP 0.033UF 100V 10% X7R AXIAL TR-14 |
| Z860201PSC | 8-BIT MICROCONTROLLER |
| Z860202PSC | Leaded Cartridge Fuse; Current Rating:600mA; Voltage Rating:250V; Fuse Terminals:Axial Lead; Fuse Type:Time Delay; Voltage Rating:250V; Body Material:Glass; Diameter:4.7mm; Fuse Size/Group:5 x 15 mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| Z860203PSC | 8-BIT MICROCONTROLLER |
| Z86116 | CAP 0.033UF 100V 10% X7R AXIAL TR-14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z8523310ASG | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10 MHZ CMOS ESCC/2 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| Z8523310FSC | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10MHz CMOS ESCC/2 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| Z8523310FSC00TR | 功能描述:IC ESCC 44QFP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:EMSCC™ 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| Z8523310FSG | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10MHz CMOS ESCC/2 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| Z8523310VSC | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10MHz CMOS ESCC/2 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。