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參數(shù)資料
| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 231/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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Application Note
Serial Communication Controller (SCC
): SDLC Mode of Operation
6-96
SDLC RECEIVE
There are several different ways to receive a SDLC packet
on the SCC; by polling, by Interrupts and by DMA. The
SCC has the following four Receive Interrupt Modes:
I
Disabled. This should be used in the Polling mode.
I
Interrupts on all received characters or Special
Conditions. This mode should be used for normal
interrupt-driven operation.
I
Interrupts on First Character or Special Condition. This
mode is intended for received data transfer by the DMA,
and enables the DMA when the interrupt is received by
the First Character of the packet.
I
Interrupt on Special Condition only. This mode allows
the DMA to free-run and keep transferring data to the
buffer. This is an ideal mode for the CMOS SCC as well
as the ESCC with Status FIFO enabled, because the
Status FIFO can give byte count and error status without
interrupting data transfer operations.
Each of the four cases is covered in this application note
except Receive Interrupt disabled. For polling, the basic
operation is identical to that used for “interrupt on all
characters or Special Condition” mode. Instead of waiting
for an interrupt, polling Reads Registers to determine if
service is needed or not.
On the SCC, data is sampled by the receiver on the rising
edge of the receive clock. Set-up and hold times for RxD
with respect to RxC are specified in the product
specifications.
In general, receiver status changes are triggered by RxC.
In the following Figures, they are shown as being
coincident with this edge — in actual practice, there are
some associated delay times (which are specified in the
data sheet).
RECEIVE INTERRUPTS ON ALL RECEIVE CHARACTERS OR SPECIAL CONDITIONS
SCC is placed in this mode by programming Bit D4-3 of
WR1 to 10. Once programmed in this mode, the SCC
generates interrupts whenever character(s) are in the
receive buffer or when Special Conditions occur. This
mode is the most common operational mode.
Notes on Figure 2:
1.
The receiver is usually in hunt mode when waiting for
a frame. When the opening flag is received, an
External/Status Interrupt is generated, indicating the
change from hunt mode to sync mode.
2.
The /SYNC output follows the state of the sync register
comparison output. The comparison is done on a bit
by bit basis, so the /SYNC pin is only active for one bit-
time. /SYNC goes active one bit-time after the last bit
of the sync character is sampled at the RxD pin.
3.
A Receive Character Available Interrupt is generated
11 bit-times 8 bits for the shifter and a 3-bit delay) after
the last bit of the character is sampled at the RxD pin.
The status bits corresponding to that character must
be read before the data character is read from the
Receive Buffer. This interrupt is for data 81H.
4.
Receive Character Available Interrupt for data 42H.
5.
Receive Character Available Interrupt for data 0FFH.
6.
Receive Character Available Interrupt for data 42H.
7.
Receive Character Available Interrupt for the first CRC
byte. The SCC treats the CRC as data, since the SCC
does not yet distinguish a difference between CRC
and data!
8.
The closing flag is recognized two bit-times before the
second CRC byte is completely assembled in the
Receive Shift Register. As soon as it is recognized, a
Special Condition interrupt is generated. The EOF bit
is set at this point and the CRC error bit can be
checked. The six least significant bits of the second
CRC byte are present at the top of the first CRC byte.
The status information must be read before the
second CRC byte is read from the buffer. The CRC
bytes should be discarded. The CRC checker is
automatically reset for the next frame.
9.
External/Status interrupt for the Sync/Hunt change.
This occurs when the SCC recognizes an Abort
(Marking line) and forces the receiver into hunt mode.
The SCC can be programmed so that the Abort itself
generates an interrupt if required. If flag idle was set,
this interrupt will not occur.
UM010901-0601
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