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參數(shù)資料
| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 40/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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SCC/ESCC User’s Manual
Interfacing the SCC/ESCC
2-21
2
2.4.6 Interrupt Acknowledge
The SCC is flexible with its interrupt method. The interrupt
may be acknowledged with a vector transferred, acknowl-
edged without a vector, or not acknowledged at all.
2.4.6.1 Interrupt Without Acknowledge
In this mode, the Interrupt Acknowledge signal does not
have to be generated. This allows a simpler hardware de-
sign that does not have to meet the interrupt acknowledge
timing. Soon after the INT goes active, the interrupt con-
troller jumps to the interrupt routine. In the interrupt routine,
the code must read RR2 from Channel B to read the vector
including status. When the vector is read from Channel B,
it always includes the status regardless of the VIS bit (WR9
bit 0). The status given will decode the highest priority in-
terrupt pending at the time it is read. The vector is not
latched so that the next read could produce a different vec-
tor if another interrupt occurs. The register is disabled from
change during the read operation to prevent an error if a
higher interrupt occurs exactly during the read operation.
Once the status is read, the interrupt routine must decode
the interrupt pending, and clear the condition. Removing
the interrupt condition clears the IP and brings /INT inac-
tive (open-drain), as long as there are no other IP bits set.
For example, writing a character to the transmit buffer
clears the transmit buffer empty IP.
When the interrupt IP, decoded from the status, is cleared,
RR2 can be read again. This allows the interrupt routine to
clear all of the IP’s within one interrupt request to the CPU.
2.4.6.2 Interrupt With Acknowledge
After the SCC brings /INT active, the CPU can respond
with a hardware acknowledge cycle by bringing /INTACK
active. After enough time has elapsed to allow the daisy
chain to settle (see AC Spec #38), the SCC sets the IUS
bit for the highest priority IP. If the No Vector bit is reset
(WR9 D1=0), the SCC then places the interrupt vector on
the data bus during a read. To speed the interrupt re-
sponse time, the SCC can modify 3 bits in the vector to in-
dicate the source of the interrupt. To include the status, the
VIS bit, WR9 D0, is set. The service routine must then
clear the interrupting condition. For example, writing a
character to the transmit buffer clears the transmit buffer
empty IP. After the interrupting condition is cleared, the
routine can read RR3 to determine if any other IP’s are set
and take the appropriate action to clear them. At the end
of the interrupt routine, a Reset IUS command (WR0) is is-
sued to unlock the daisy chain and allow lower-priority in-
terrupt requests. This is the only way, short of a software
or hardware reset, that an IUS bit is reset.
If the No Vector bit is set (WR9 D1=1), the SCC will not
place the vector on the data bus. An interrupt controller
must then vector the code to the interrupt routine. The in-
terrupt routine reads RR2 from Channel B to read the sta-
tus. This is similar to an interrupt without an acknowledge,
except the IUS is set and the vector will not change until
the Reset IUS command in RR0 is issued.
2.4.6.3 Software Interrupt Acknowledge (CMOS/ESCC)
An interrupt acknowledge cycle can be done in software
for those applications which use an external interrupt con-
troller or which cannot generate the /INTACK signal with
the required timing. If WR9 D5 is set, reading register two,
RR2, results in an interrupt acknowledge cycle to be exe-
cuted internally. Like a hardware INTACK cycle,
a software acknowledge causes the /INT pin to return
High, the IEO pin to go Low and the IUS latch to be set for
the highest priority interrupt pending.
As when the hardware /INTACK signal is used, a software
acknowledge cycle requires that a Reset Highest IUS
command be issued in the interrupt service routine. If RR2
is read from Channel A, the unmodified vector is returned.
If RR2 is read from Channel B, then the vector is modified
to indicate the source of the interrupt. The Vector Includes
Status (VIS) and No Vector (NV) bits in WR9 are ignored
when bit D5 is set to 1.
2.4.7 The Receiver Interrupt
The sources of receive interrupts consist of Receive Char-
acter Available and Special Receive Condition. The Spe-
cial Receive Condition can be subdivided into Receive
Overrun, Framing Error (Asynchronous) or End of Frame
(SDLC). In addition, a parity error can be a special receive
condition by programming.
As shown in Figure 2-14, Receive Interrupt mode is
controlled by three bits in WR1. Two of these bits, D4 and
D3, select the interrupt mode; the third bit, D2, is a modifier
for the various modes. On the ESCC, WR7' bit D2 affects
the receiver interrupt operation mode as well. If the
interrupt capability of the receiver in the SCC is not
required, polling may be used. This is selected by disabling
receive interrupts and polling the Receiver Character
Available bit in RR0. When this bit indicates that a received
character has reached the exit location (CPU side) of the
FIFO, the status in RR1 should be checked and then the
data should be read. If status is checked, it must be done
before the data is read, because the act of reading the data
pops both the data and error FIFOs. Another way of polling
SCC is to enable one of the interrupt modes and then reset
the MIE bit in WR9. The processor may then poll the IP bits
in RR3A to determine when receive characters are
available.
UM010901-0601
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