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| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁(yè)數(shù)： | 120/317頁(yè) |
| 文件大小： | 3201K |
| 代理商： | Z85233 |
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SCC/ESCC User’s Manual
Register Descriptions
5-13
5
5.2.10 Write Register 7 Prime (85C30 only)
This Register is used only with the CMOS 85C30 SCC.
WR7' is written to by first setting bit D0 of WR15 to 1, and
pointing to WR7 as normal. All writes to register 7 will be
to WR7' so long as WR D0 is set. WR 15 bit D0 must be
reset to 0 to address the sync register, WR7. If bit D6 of
WR7' was set during the write, then WR7' can be read by
accessing to RR14. The features remain enabled until
specifically disabled, or disabled by a hardware or
software reset. Figure 5-10a. shows WR7'.
Bit 7: Reserved.
This bit is reserved and must be programmed as 0.
Bit 6: Extended Read Enable bit
This bit enables the Extended Read. Setting this bit en-
ables the reading of WR3, WR4, WR5, WR7' and WR10.
When this feature is enabled, these registers can be ac-
cessed by reading RR9, RR4, RR5, RR14, and RR11, re-
spectively. When this feature is not enabled, register ac-
cess is to the SCC. In this case, read to these register
locations returns RR13, RR0, RR1, RR10, and RR15 re-
spectively.
Bit 5: Receive Complete CRC
On this version, with this bit set to 1, the 2nd byte of the
CRC is received completely. This feature is ideal for appli-
cations which require a 2nd CRC byte for complete data;
for example, a protocol analyzer or applications using oth-
er than CRC-CCITT CRC (i.e., 32bit CRC).
In SDLC mode of operation, the CMOS SCC, on this bit is
programmed as 0. In this case on the EOF condition (when
the closing flag is detected), the contents of the Receive
Shift Register are transferred to the Receive Data FIFO re-
gardless of the number of bits assembled. Because of the
three-bit delay path between the sync register and the Re-
ceive Shift register, the last two bits of the 2nd byte of the
CRC are never transferred to the Receive Data FIFO. The
data is actually formed with the six Least Significant Bits of
the 2nd CRC byte.
Bit 4: /DTR//REQ Timing Fast Mode.
If this bit is set and the /DTR//REQ pin is used for Request
Mode (WR14, bit D2=1), the deactivation of the
/DTR//REQ pin is identical to the /W//REQ pin, which is
triggered on the falling edge of the /WR signal, and the
/DTR//REQ pin goes inactive below 200 ns (this number
varies depending on the speed grade of the device). When
this bit is reset to 0, the deactivation time for the
/DTR//REQ pin is 4TcPc.
Bit 3: Force TxD High.
In the SDLC mode of operation with the NRZI encoding
mode, there is an option to force TxD High. If bit D0 of
WR15 is set to 1, bit D3 of WR7' can be used to set TxD
pin High.
Note that the operation of this bit is independent of the Tx
Enable bit in WR5 is used to control transmission activities,
whereas bit D3 of WR7' acts as a pseudo transmitter may
actually be mark or flag idling. Care must be exercised
when setting this bit because any character being trans-
mitted at the time that bit is set is “chopped off”; data writ-
ten to the Transmit Buffer while this bit is set is lost.
Bit 2: Auto /RTS pin Deactivation
This bit controls the timing of the deassertion of the /RTS
pin. If this device is programmed for SDLC mode and Flag-
On-Underrun (WR10 D2=0), this bit is set and the RTS bit
is reset. The /RTS is deasserted automatically at the last
bit of the closing flag, triggered by the rising edge of the
TxC. If this bit is reset to 0, the /RTS pin follows the state
programmed in WR5 bit D1.
Bit 1: Automatic Tx Underrun/EOM Latch Reset
If this bit is set, this version automatically resets the Tx Un-
derrun/EOM latch and presets the transmit CRC generator
to its programmed preset state (the values set in WR5 D2
& WR10 D7). This removes the requirement to issue the
Reset Tx Underrun/EOM latch command. Also, this fea-
ture enables a write transmit data before enabling the
transmitter.
Bit 0: Automatic SDLC Opening Flag Transmission.
If this bit is set, the device automatically transmits an
SDLC opening flag before transmitting data. This removes
the requirement to reset the mark idle bit (WR10, bit D3)
before writing data to the transmitter, or having to enable
the transmitter before writing data to the Transmit buffer.
Also, this feature enables a write transmit data before en-
abling the transmitter.
5.2.11 Write Register 8 (Transmit Buffer)
WR8 is the transmit buffer register.
Figure 5-10a. Write Register 7 Prime (WR7')
D7 D6 D5
D4
D3
D2
D1
D0
WR7' Prime
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Force TxD High
/DTR//REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)
UM010901-0601
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