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參數(shù)資料
| 型號： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 129/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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SCC/ESCC User’s Manual
Register Descriptions
5-22
5.3 READ REGISTERS
(Continued)
Bit 7: Break/Abort status
In the Asynchronous mode, this bit is set when a Break se-
quence (null character plus framing error) is detected in
the receive data stream. This bit is reset when the se-
quence is terminated, leaving a single null character in the
Receive FIFO. This character is read and discarded. In
SDLC mode, this bit is set by the detection of an Abort se-
quence (seven or more 1s), then reset automatically at the
termination of the Abort sequence. In either case, if the
Break/Abort IE bit is set, an External/Status interrupt is ini-
tiated. Unlike the remainder of the External/Status bits,
both transitions are guaranteed to cause an External/Sta-
tus interrupt, even if another External/Status interrupt is
pending at the time these transitions occur. This procedure
is necessary because Abort or Break conditions may not
persist.
Bit 6: Transmit Underrun/EOM status
This bit is set by a channel or hardware reset when the
transmitter is disabled or a Send Abort command is issued.
This bit is only reset by the reset Tx Underrun/EOM Latch
command in WR0. When the Transmit Underrun occurs,
this bit is set and causes an External/Status interrupt (if the
Tx Underrun/EOM IE bit is set).
Only the 0-to-1 transition of this bit causes an interrupt.
This bit is always 1 in Asynchronous mode, unless a reset
Tx Underrun/EOM Latch command has been erroneously
issued. In this case, the Send Abort command can be used
to set the bit to one and at the same time cause an Exter-
nal/Status interrupt.
Bit 5: Clear to Send pin status
If the CTS IE bit in WR15 is set, this bit indicates the state
of the /CTS pin while no interrupt is pending, latches the
state of the /CTS pin and generates an External/Status in-
terrupt. Any odd number of transitions on the /CTS pin
causes another External/Status interrupt condition. If the
CTS IE bit is reset, it merely reports the current unlatched
state of the /CTS pin.
Bit 4: Sync/Hunt status
The operation of this bit is similar to that of the CTS bit, ex-
cept that the condition monitored by the bit varies depend-
ing on the mode in which the SCC is operating.
When the XTAL oscillator option is selected in asynchro-
nous modes, this bit is forced to 0 (no External/Status in-
terrupt is generated). Selecting the XTAL oscillator in syn-
chronous or SDLC modes has no effect on the operation
of this bit.
The XTAL oscillator should not be selected in External
Sync mode.
In Asynchronous mode, the operation of this bit is identical
to that of the CTS status bit, except that this bit reports the
state of the /SYNC pin.
In External sync mode the /SYNC pin is used by external
logic to signal character synchronization. When the Enter
Hunt Mode command is issued in External Sync mode, the
/SYNC pin must be held High by the external sync logic un-
til character synchronization is achieved. A High on the
/SYNC pin holds the Sync/Hunt bit in the reset condition.
When external synchronization is achieved, /SYNC is driv-
en Low on the second rising edge of the Receive Clock af-
ter the last rising edge of the Receive Clock on which the
last bit of the receive character was received. Once /SYNC
is forced Low, it is good practice to keep it Low until the
CPU informs the external sync logic that synchronization is
lost or that a new message is about to start. Both transi-
tions on the /SYNC pin cause External/Status interrupts if
the Sync/Hunt IE bit is set to 1.
The Enter Hunt Mode command should be issued when-
ever character synchronization is lost. At the same time,
the CPU should inform the external logic that character
synchronization has been lost and that the SCC is waiting
for /SYNC to become active.
In the Monosync and Bisync Receive modes, the
Sync/Hunt status bit is initially set to 1 by the Enter Hunt
Mode command. The Sync/Hunt bit is reset when the SCC
established character synchronization. Both transitions
cause External/Status interrupts if the Sync/Hunt IE bit is
set. When the CPU detects the end of message or the loss
of character synchronization, the Enter Hunt Mode com-
mand should be issued to set the Sync/Hunt bit and cause
an External/Status interrupt. In this mode, the /SYNC pin
is an output, which goes Low every time a sync pattern is
detected in the data stream.
In the SDLC modes, the Sync/Hunt bit is initially set by
the Enter Hunt Mode command or when the receiver is
disabled. It is reset when the opening flag of the first
frame is detected by the SCC. An External/Status inter-
rupt is also generated if the Sync/Hunt IE bit is set. Unlike
the Monosync and Bisync modes, once the Sync/Hunt bit
is reset in SDLC mode, it does not need to be set when
the end of the frame is detected. The SCC automatically
maintains synchronization. The only way the Sync/Hunt
bit is set again is by the Enter Hunt Mode command or by
disabling the receiver.
Bit 3: Data Carrier Detect status
If the DCD IE bit in WR15 is set, this bit indicates the state
of the /DCD pin the last time the Enabled External/Status
bits changed. Any transition on the /DCD pin, while no in-
terrupt is pending, latches the state of the /DCD pin and
UM010901-0601
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