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| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁(yè)數(shù)： | 271/317頁(yè) |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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Application Note
Technical Considerations When Implementing LocalTalk Link Access Protocol
6-136
TRANSMITTING A LLAP FRAME
Listing 2 shows the assembler code for subroutine txenq,
which sends an lapENQ frame on the line once the system
has determined that the line is quiet. Note that this routine
can easily be generalized to send any frame.
The first responsibility of txenq is to send the sync pulse
required by the CSMA/CA protocol. To do this, txenq sets
the /RTS pin active low, enabling the transmitter drivers,
and then sets it high again to disable them. In order to
satisfy the requirements of the CSMA/CA protocol, the
transmitter drivers must remain off for at least one bit time
(4.3
μ
sec) to guarantee that all the receivers see at least
one transition. Our routine satisfies this requirement
because the two ld instructions (7 T states each), the two
nop instructions (4 T states each) and the two “out”
instructions (11 T states each) required to set the /RTS line
high, take more than 4.3
μ
sec to execute on the 10 MHz
Z80181. The transmitter drivers must then remain off for at
least two bit times in order to ensure that all receivers lose
clock; again, the routine depends upon the time required
to execute the instructions before we turn the transmitter
drivers on again.
After sending the sync pulse and waiting the required
period of silence, txenq turns on the transmitter drivers to
send the frame. Now, the routine must wait while the SCC
sends out the leading flags. This takes 16 bit times, and
since the SCC does not tell when this has happened, the
transmit routine has no choice but to time this. Our routine
does this by calling bit time, which is discussed below.
When the two flags have been transmitted, the first data
byte is written to the data register of the SCC. Thereafter,
the routine polls the SCC status register, and when that
register shows the transmit buffer register is empty, the
routine sends the next data character. This polling method
can obviously be replaced by an interrupt routine that is
entered when the transmit buffer is empty or by setting up
the Z80181’s DMA to send characters on demand to the
SCC.
After the first data byte is transmitted, the txenq routine
sets the SCC to mark on idle so that the abort is sent when
the frame is over. This operation can be done any time
after the first data character has been placed in the
transmit buffer and before the trailing flag is shifted out.
Txenq asserts this mark on idle command after the first
character is placed in the transmit buffer so that LLAP has
control and that no issues of latency may arise (particularly
in designs using interrupt or DMA).
After the last data byte is written to the SCC, the transmit
routine must wait while the last data byte (the one that the
SCC had just sent to shifter), the two CRC bytes, one flag
byte and 12 to 18 bit times of marking are transmitted. This
total of 44 to 50 bit times is again timed by bittime. When
bittime indicates that enough time has elapsed, the
transmitter drivers are turned off.
Since our hardware includes connecting the output of the
baud rate generator to the input of counter/timer 1 on the
Z80181, that counter timer counts the bit times. The bit
time routine feeds an appropriate count value into the
counter and enables an interrupt routine to receive control
when the count expires. The interrupt routine ctc1int,
shown in Listing 4, sets the timeflag which the transmit
routine polls.
Note that the call to bittime, the interrupt routine, the polling
code and the length of time it takes to write to the SCC
registers after a polling loop is exited, all take up a time that
can be a significant number of bits. In order to do these
timings accurately, calculate the number of PCLK cycles
required to execute these pieces of code and to adjust the
counter value that bittime requires. This adjustment is
dependent on the hardware configuration and on the exact
implementation details of the code.
Note, incidentally, that software must put the entire frame
into the transmit register, including the addresses. The
SCC does not generate addresses even when set in WR6.
RECEIVING LLAP FRAMES
In the experiments, the interrupt routines were used to
receive characters and to handle special conditions when
the frame is complete. Listing 3 shows the interrupt
handlers that are entered when the SCC receives a
character and when the SCC interrupts for a special
condition (typically, end of frame). As with transmission, it
is obvious that we could receive characters by polling the
SCC (using up all available CPU cycles) or by using DMA
(using up very few). It is estimated that the recint routine
uses up about 1/3 of the available 34
bit times) cycles on a 10 MHz processor.
μ
sec (4.3
μ
sec x 8-
The recint routine moves each character as it is received
from the SCC to a memory buffer and increments the
buffer pointer. The frame’s data length is checked to make
certain that the maximum allowable frame size is not
exceeded.
The spcond interrupt handler checks the status of the SCC
to find out what has happened. The presence on an
overrun condition or a CRC error is flagged as a receive
frame error.
UM010901-0601
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