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參數(shù)資料
| 型號： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 81/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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SCC/ESCC User’s Manual
Data Communication Modes
4-6
4.2 ASYNCHRONOUS MODE
(Continued)
bit, bit D0 of RR1, can be polled to determine when the last
bit of transmit data has cleared the TxD pin.
The number of transmit interrupts can be minimized by set-
ting bit D5 of WR7' to one and writing four bytes to the
transmitter for each transmit interrupt. This requires that
the system response to interrupt is less than the time it
takes to transmit one byte at the programmed baud rate. If
the system’s interrupt response time is too long to use this
feature, bit D5 of WR7' should be reset to 0. Then, poll the
TBE bit and poll after each data write to test if there is
space in the Transmit FIFO for more data.
For details about the transmit DMA and transmit interrupts,
refer to Section 2.4.8 “Transmit Interrupt and Transmit
Buffer Empty bit”.
4.2.2 Asynchronous Receive
Asynchronous mode is selected by specifying the number
of stop bits per character in bits D3 and D2 of WR4. This
selection applies only to the transmitter, however, as the
receiver always checks for one stop bit. If after character
assembly the receiver finds this stop bit to be a 0, the
Framing Error bit in the receive error FIFO is set at the
same time that the character is transferred to the receive
data FIFO. This error bit accompanies the data to the exit
location (CPU side) of the Receive FIFO, where it is a spe-
cial receive condition. The Framing Error bit is not latched,
so it must be read in RR1 before the accompanying data
is read.
The number of bits per character is controlled by bits D7
and D6 of WR3. Five, six, seven or eight bits per character
may be selected via these two bits. Data is right justified
with the unused bits set to 1s. An additional bit, carrying
parity information, may be selected by setting bit D0 of
WR4 to 1. Note that this also enables parity for the trans-
mitter. The parity sense is selected by bit D1 of WR4. If this
bit is set to 1, the received character is checked for even
parity, and if set to 0, the received character is checked for
odd parity. The additional bit per character that is parity is
transferred to the receive data FIFO along with the data, if
the data plus parity is eight bits or less. The parity error bit
in the receive error FIFO may be programmed to cause
special receive interrupts by setting bit D2 of WR1 to 1.
Once set, this error bit is latched and remains active until
an Error Reset command has been issued.
Since errors apply to specific characters, it is necessary
that error information moves alongside the data that it re-
fers to. This is implemented in the SCC with an error FIFO
in parallel with the data FIFO. The three error conditions
that the receiver checks for in Asynchronous mode are:
I
Framing errors—When a character’s stop bit is a 0.
I
Parity errors—The parity bit of a character disagrees
with the sense programmed in WR4.
I
Overrun errors—When the Receive FIFO overflows.
If interrupts are not used to transfer data, the Parity Error,
Framing Error, and Overrun Error bits in RR1 should be
checked before the data is removed from the receive data
FIFO, because reading data pops up the error information
stored in the Error FIFO.
The SCC may be programmed to accept a receive clock
that is one, sixteen, thirty-two, or sixty-four times the data
rate. This is selected by bits D7 and D6 in WR4. The 1X
mode is used when bit synchronization external to the re-
ceived clock is present (i.e., the clock recovery circuit, or
active receive clock from the sender side). The 1X mode is
the only mode in which a data encoding method other than
NRZ may be used. The clock factor is common to the re-
ceiver and transmitter.
The break condition is continuous 0s, as opposed to the
usual continuous ones during an idle condition. The SCC
recognizes the Break condition upon seeing a null charac-
ter (all 0s) plus a framing error. Upon recognizing this se-
quence, the Break bit in RR0 is set and remains set until a
1 is received. At this point, the break condition is no longer
present. At the termination of a break, the receive data
FIFO contains a single null character, which should be
read and discarded. The framing error bit will not be set for
this character, but if odd parity has been selected, the Par-
ity Error bit is set.
Note:
contains a switch that is not debounced to generate
breaks. If this is the case, switch bounce may cause multi-
ple breaks to be recognized by the SCC, with additional
characters assembled in the receive data FIFO and the
possibility of a receive overrun condition being latched.
Caution should be exercised if the receive data line
The SCC provides up to three modem control signals as-
sociated with the receiver; /SYNC, /DTR//REQ,
and /DCD.
The /SYNC pin is a general purpose input whose state is
reported in the Sync/Hunt bit in RR0. If the crystal oscillator
is enabled, this pin is not available and the Sync/Hunt bit
is forced to 0. Otherwise, the /SYNC pin may be used to
carry the Ring Indicator signal.
The /DTR//REQ pin carries the inverted state of the DTR
bit (D7) in WR5 unless this pin has been programmed to
carry a DMA request signal.
The /DCD pin is ordinarily a simple input to the DCD bit in
RR0. However, if the Auto Enables mode is selected by
setting D5 of WR3 to 1, this pin becomes an enable for the
UM010901-0601
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