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參數(shù)資料
| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 106/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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SCC/ESCC User’s Manual
Data Communication Modes
4-31
4
If SDLC loop is deselected, the SCC is designed to exit
from the loop gracefully. When the SDLC Loop mode is de-
selected by writing to WR10, the SCC waits until the next
polling cycle to remove the one-bit time delay.
If a polling cycle is in progress at the time the command is
written, the SCC finishes sending any message that it is
transmitting, ends with an EOP, and disconnects TxD from
RxD. If no message was in progress, the SCC immediately
disconnects TxD from RxD.
Once the SCC is not sending on the loop, exiting from the
loop is accomplished by setting the Loop Mode bit in
WR10 to 0, and at the same time writing the Abort/Flag on
Underrun and Mark/Flag idle bits with the desired values.
The SCC will revert to normal SDLC operation as soon as
an EOP is received, or immediately if the receiver is al-
ready in Hunt mode because of the receipt of an EOP.
To ensure proper loop operation after the SCC goes off the
loop, and until the external relays take the SCC completely
out of the loop, the SCC should be programmed for Mark
idle instead of Flag idle. When the SCC goes off the loop,
the On-Loop bit is reset.
Note:
With NRZI encoding, removing the stations from the
loop (removing the one-bit time delay) may cause prob-
lems further down the loop because of extraneous transi-
tions on the line. The SCC avoids this problem by making
transparent adjustments at the end of each frame it sends
in response to an EOP. A response frame from the SCC is
terminated by a flag and EOP. Normally, the flag and the
EOP share a zero, but if such sharing would cause the
RxD and TxD pins to be of opposite polarity after the EOP,
the SCC adds another zero between the flag and the EOP.
This causes an extra line transition so that RxD and TxD
are identical after the EOP is sent. This extra zero is com-
pletely transparent because it only means that the flag and
the EOP no longer share a zero. All that a proper loop exit
needs, therefore, is the removal of the one-bit delay.
The SCC allows the user the option of using NRZI in SDLC
Loop mode by programming WR10 appropriately. With
NRZI encoding, the outputs of secondary stations in the
loop are inverted from their inputs because of messages
that they have transmitted.
Subsections 4.4.4.1 and 4.4.4.2 discuss the SDLC Loop
Mode in Receive and Transmit.
4.4.4.1 SDLC Loop Mode Receive
SDLC Loop mode is quite similar to SDLC mode except
that two additional control bits are used. They are the Loop
Mode bit (D1) and the Go-Active-On-Poll bit (D4) in WR10.
In addition to these two extra control bits, there are also
two status bits in RR10. They are the On Loop bit (D1) and
the Loop Sending bit (D4).
Before Loop mode is selected, both the receiver and trans-
mitter have to be completely initialized for SDLC operation.
Once this is done, Loop mode is selected by setting bit D1
of WR10 to 1. At this point, the SCC connects TxD to RxD
with only gate delays in the path. At the same time, a flag
is loaded into the Transmit Shift register and is shifted to
the end of the zero inserter, ready for transmission. The
SCC remains in this state until the Go-Active-On-Poll bit
(D4) in WR10 is set to 1. When this bit is set to 1, the re-
ceiver begins looking for a sequence of seven consecutive
1s, indicating either an EOP or an idle line. When the re-
ceiver detects this condition, the Break/Abort bit in RR0 is
set to 1, and a one-bit time delay is inserted in the path
from RxD to TxD.
The On-Loop bit in RR10 is also set to 1 at this time, and
the receiver enters the Hunt mode. The SCC cannot trans-
mit on the loop until a flag is received (causing the receiver
to leave Hunt mode) and another EOP (bit pattern
11111110) is received. The SCC is now on the loop and
capable of transmitting on the loop. As soon as this status
is recognized by the processor, the Go-Active-On-Poll bit
in WR10 is set to 0 to prevent the SCC from transmitting
on the loop without a processor acknowledgment.
4.4.4.2 SDLC Loop Mode Transmit
To transmit a message on the loop, the Go-Active-On-Poll
bit in WR10 must be set to 1. Once this is done, the SCC
changes the next received EOP into a Flag and begins
transmitting on the loop.
When the EOP is received, the Break/Abort and Hunt bits
in RR0 are set to 1, and the Loop Sending bit in RR10 is
also set to 1. Data to be transmitted is written after the Go-
Active-On-Poll bit has been set or after the receiver enters
Hunt mode.
If the data is written immediately after the Go-Active-On-
Poll bit has been set, the SCC only inserts one flag after
the EOP is changed into a flag. If the data is not written un-
til after the receiver enters the Hunt mode, the flags are
transmitted until the data is written. If only one frame is to
be transmitted on the loop in response to an EOP, the pro-
cessor must set the Go Active on Poll bit to 0 before the
last data is written to the transmitter. In this case, the trans-
mitter closes the frame with a single flag and then reverts
to the one-bit delay.
The Loop Sending bit in RR10 is set to 0 when the closing
Flag has been sent. If more than one frame is to be trans-
mitted, the Go-Active-On-Poll bit should not be set to 0 un-
til the last frame is being sent. If this bit is not set to 0 be-
fore the end of a frame, the transmitter sends Flags until
either more data is written to the transmitter, or until the
Go-Active-On-Poll bit is set to 0. Note that the state of the
Abort/Flag on Underrun and Mark/Flag idle bits in WR10 is
ignored by the SCC in SDLC Loop mode.
UM010901-0601
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