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| 型號： | Z85230 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 95/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85230 |
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SCC/ESCC User’s Manual
Data Communication Modes
4-20
4.3 BYTE-ORIENTED SYNCHRONOUS MODE
(Continued)
Section 2.4.8 “Transmit Interrupts and Transmit Buffer
Empty bit”.
The character length may be changed on the fly, but the
desired length must be selected before the character is
loaded into the Transmit Shift register from the transmit
data FIFO. The easiest way to ensure this is to write to
WR5 to change the character length before writing the
data to the transmit buffer. Note that although the charac-
ter can be any length, most protocols specify the ad-
dress/control field as 8-bit fields. The SCC receiver
checks the address field as 8-bit, if address search mode
is enabled.
Only the CRC-CCITT polynomial is used in SDLC mode.
This is selected by setting bit D2 in WR5 to 0. This bit con-
trols the selection for both the transmitter and receiver.
The initial state of the generator and checker is controlled
by bit D7 of WR10. When this bit is set to 1, both the gen-
erator and checker have an initial value of all 1s, and if this
bit is set to 0, the initial values are all 0s.
The SCC does not automatically preset the CRC genera-
tor, so this is done in software. This is accomplished by is-
suing the Reset Tx CRC command, which is encoded in
bits D7 and D6 of WR0. For proper results, this command
is issued while the transmitter is enabled and idling. If the
CRC is to be used, the transmit CRC generator is enabled
by setting bit D0 of WR5 to 1. The CRC is normally calcu-
lated on all characters between opening and closing flags,
so this bit is usually set to 1 at initialization and never
changed. On the 85X30 with Auto EOM Latch reset mode
enabled (WR7' bit D1=1), resetting of the CRC generator
is done automatically.
Enabling the CRC generator is not sufficient to control the
transmission of the CRC. In the SCC, this function is con-
trolled by Tx Underrun/EOM bit, which may be reset by the
processor and set by SCC. On the 85X30 with Auto EOM
Reset mode enabled (WR7' bit D1=1), resetting of the Tx
Underrun/EOM Latch is done automatically.
Ordinarily, a frame is terminated with a CRC and a flag, but
the SCC may be programmed to send an abort and a flag
in place of the CRC. This option allows the SCC to abort a
frame transmission in progress if the transmitter is acci-
dentally allowed to underrun. This is controlled by the
Abort/Flag on Underrun bit (D2) in WR10. When this bit is
set to 1, the transmitter will send an abort and a flag in
place of the CRC when an underrun occurs. The frame is
terminated normally with a CRC and a flag if this bit is 0.
The SCC is also able to send an abort by a command from
the processor. When the Send Abort command is issued
in WR0, the transmitter sends eight consecutive 1s and
then idles. Since up to five consecutive 1s may be sent pri-
or to the command being issued, a Send Abort causes a
sequence of from eight to thirteen 1s to be transmitted.
The Send Abort command also clears the transmit
data FIFO.
When transmitting in SDLC mode, note that all data pass-
es through the zero inserter, which adds an extra five bit
times of delay between the Transmit Shift register and the
TxD Pin.
When the transmitter underruns (both the Transmit
FIFO and Transmit Shift register are empty), the state of
the Tx Underrun/EOM bit determines the action taken by
the SCC.
If the Tx Underrun/EOM bit is set to 1 when the underrun
occurs, the transmitter sends flags without sending the
CRC. If this bit is reset to 0 when the underrun occurs, the
transmitter sends either the accumulated CRC followed by
flags, or an abort followed by flags, depending on the state
of the Abort/Flag on the Underrun bit in the WR10, bit D1.
A summary is shown in Table 4-9.
The Reset Tx Underrun/EOM Latch command is encoded
in bits D7 and D6 of WR0.
The SCC sets the Tx Underrun/EOM latch when the CRC
or abort is loaded into the shift register for transmission.
This event can cause an interrupt, and the status of the Tx
Underrun/EOM latch can be read in RR0.
Resetting the Tx Underrun/EOM latch is done by the pro-
cessor via the command encoded in bits D7 and D6 of
WR0. On the 85X30, this also can be accomplished by set-
ting WR7' bit D1 for Auto Tx Underrun/EOM Latch Reset
mode enabled. For correct transmission of the CRC at the
end of a frame, this command must be issued after the first
character is written to the SCC but before the transmitter
underruns after the last character written to the SCC. The
command is usually issued immediately after the first char-
acter is written to the SCC so that the abort or CRC is sent
if an underrun occurs inadvertently. The Abort/Flag on Un-
derrun bit (D2) in WR10 is usually set to 1 at the same time
as the Tx Underrun/EOM bit is reset so that an abort is
sent if the transmitter underruns. The bit is then set to 0
Table 4-9. ESCC Action Taken on Tx Underrun
Tx Underrun
/EOM Latch Bit
0
Abort/Flag
0
Action taken by
ESCC upon
transmit underrun
Sends CRC followed
by flag
Sends abort followed
by flag
Sends flag
0
1
1
x
UM010901-0601
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