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| 型號： | Z85230 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 38/317頁 |
| 文件大小： | 3201K |
| 代理商： | Z85230 |
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SCC/ESCC User’s Manual
Interfacing the SCC/ESCC
2-19
2
2.4.5 Daisy-Chain Resolution
The six sources of interrupt in the SCC are prioritized in a
fixed order via a daisy chain; provision is made, via the IEI
and IEO pins, for use of an external daisy chain as well. All
Channel A interrupts are higher priority than any
Channel B interrupts, with the receiver, transmitter, and
External/Status interrupts prioritized in that order within
each channel. The SCC requests an interrupt by pulling
the /INT pin Low from its open-drain state. This is con-
trolled by the IP bits and the IEI input, among other things.
A flowchart of the interrupt sequence for the SCC is shown
in Figure 2-13.
The internal daisy chain links the six sources of interrupt in
a fixed order, chaining the IUS bits for each source. While
an IUS bit is set, all lower priority interrupt requests are
masked off, thus preventing lower priority interrupts, but
still allowing higher priority interrupts to occur. Also, during
an interrupt acknowledge cycle the IP bits are gated into
the daisy chain. This insures that the highest priority IP is
selected to set IUS. The internal daisy chain may be con-
trolled by the MIE bit in WR9. This bit, when reset, has the
same effect as pulling the IEI pin Low, thus disabling all in-
terrupt requests.
2.4.5.1 External Daisy-Chain Operations
The SCC generates an interrupt request by pulling /INT
Low, but only if such interrupt requests are enabled
(IE is 1, MIE is 1) and all of the following conditions occur:
I
IP is set without a higher priority IUS being set
I
No higher priority IUS is being set
I
No higher priority interrupt is being serviced (IEI is High)
I
No interrupt acknowledge transaction is taking place
IEO is not pulled Low by the SCC at this time, but instead
continues to follow IEI until an interrupt acknowledge
transaction occurs. Some time after /INT has been pulled
Low, the processor initiates an Interrupt Acknowledge
transaction. Between the time the SCC recognizes that an
Interrupt Acknowledge cycle is in progress and the time
during the acknowledge that the processor requests an in-
terrupt vector, the IEI/IEO daisy chain settles. Any periph-
eral in the daisy chain having an Interrupt Pending (IP is 1)
or an Interrupt-Under-Service (IUS is 1) holds its IEO line
Low and all others make IEO follow IEI.
When the processor requests an interrupt vector, only the
highest priority interrupt source with a pending interrupt
(IP is 1) has its IEI input High, its IE bit set to 1, and its IUS
bit set to 0. This is the interrupt source being acknowl-
edged, and at this point it sets its IUS bit to 1. If its NV bit
is 0, the SCC identifies itself by placing the interrupt vector
from WR2 on the data bus. If the NV bit is 1, the SCC data
bus remains floating, allowing external logic to supply a
vector. If the VIS bit in the SCC is 1, the vector also con-
tains status information, encoded as shown in Table 2-9,
which further describes the nature of the SCC interrupt.
If the VIS bit is 0, the vector held in WR2 is returned without
modification. If the SCC is programmed to include status
information in the vector, this status may be encoded and
placed in either bits 1-3 or in bits 4-6. This operation is
selected by programming the Status High/Status Low bit in
WR9. At the end of the interrupt service routine, the
processor should issue the Reset Highest IUS command
to unlock the daisy chain and allow lower priority interrupt
requests. The IP is reset during the interrupt service
routine, either directly by command or indirectly through
some action taken by the processor. The external daisy
chain may be controlled by the DLC bit in WR9. This bit,
when set, forces IEO Low, disabling all lower priority
devices.
Table 2-9. Interrupt Vector Modification
V3
V2
V1
Status High/Status Low = 0
V4
0
0
0
0
1
1
1
1
V5
0
0
1
1
0
0
1
1
V6
0
1
0
1
0
1
0
1
Status High/Status Low = 1
Ch B Transmit Buffer Empty
Ch B External/Status Change
Ch B Receive Character Avail
Ch B Special Receive Condition
Ch A Transmit Buffer Empty
Ch A External/Status Change
Ch A Receive Character Avail
Ch A Special Receive Condition
UM010901-0601
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