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| 型號： | Z85230 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 116/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85230 |
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SCC/ESCC User’s Manual
Register Descriptions
5-9
5
64X Mode (11).
With this bit combination in External Sync mode, both the
receiver and transmitter are placed in SDLC mode. The only
variation from normal SDLC operation is that the /SYNC pin
is used to start or stop the reception of a frame by forcing the
receiver to act as though a flag had been received.
The clock rate is 64 times the data rate.
Bits 5 and 4: SYNC Mode selection bits 1 and 0
These two bits select the various options for character syn-
chronization. They are ignored unless synchronous modes
are selected in the stop bits field of this register.
Monosync Mode (00).
character synchronization by matching the character
stored in WR7 with an identical character in the received
data stream. The transmitter uses the character stored in
WR6 as a time fill. The sync character is either six or eight
bits, depending on the state of the 6-bit/8-bit sync bit in
WR10. If the Sync Character Load Inhibit bit is set, the re-
ceiver strips the contents of WR6 from the data stream if
received within character boundaries.
In this mode, the receiver achieves
Bisync Mode (01).
The concatenation of WR7 with WR6
is used for receiver synchronization and as a time fill by the
transmitter. The sync character is 12 or 16 bits in the re-
ceiver, depending on the state of the 6-bit/8-bit sync bit in
WR10. The transmitted character is always 16 bits.
SDLC Mode (10).
In this mode, SDLC is selected and re-
quires a Flag (01111110) to be written to WR7. The receiv-
er address field is written to WR6. The SDLC CRC polyno-
mial is also selected (WR5) in SDLC mode.
External Sync Mode (11).
In this mode, the SCC expects
external logic to signal character synchronization via the
/SYNC pin. If the crystal oscillator option is selected (in
WR11), the internal /SYNC signal is forced to 0. In this
mode, the transmitter is in Monosync mode using the con-
tents of WR6 as the time fill with the sync character length
specified by the 6-bit/8-bit Sync bit in WR10.
Bits 3 and 2: Stop Bits selection, bits 1 and 0
These bits determine the number of stop bits added to
each asynchronous character that is transmitted. The re-
ceiver always checks for one stop bit in Asynchronous
mode. A special mode specifies that a Synchronous mode
is to be selected. D2 is always set to 1 by a channel or
hardware reset to ensure that the /SYNC pin is in a known
state after a reset.
Synchronous Modes Enable (00).
This bit combination
selects one of the synchronous modes specified by bits
D4, D5, D6, and D7 of this register and forces the 1X Clock
mode internally.
1 Stop Bit/Character (01).
This bit selects Asynchronous
mode with one stop bit per character.
1 1/2 Stop Bits/Character (10).
These bits select Asyn-
chronous mode with 1-1/2 stop bits per character. This
mode is not used with the 1X clock mode.
2 Stop Bits/Character (11).
These bits select Asynchro-
nous mode with two stop bits per transmitted character
and checks for one received stop bit.
Bit 1: Parity Even//Odd select bit
This bit determines whether parity is checked as even or
odd. A 1 programmed here selects even parity, and a 0 se-
lects odd parity. This bit is ignored if the Parity enable bit
is not set.
Bit 0: Parity Enable
When this bit is set, an additional bit position beyond those
specified in the bits/character control is added to the trans-
mitted data and is expected in the receive data. The Re-
ceived Parity bit is transferred to the CPU as part of the data
unless eight bits per character is selected in the receiver.
5.2.6 Write Register 5 (Transmit Parameters
and Controls)
WR5 contains control bits that affect the operation of the
transmitter. D2 affects both the transmitter and the
receiver. Bit positions for WR5 are shown in Figure 5-7. On
the 85X30 with the Extended Read option enabled, this
register is read as RR5.
Bit 7: Data Terminal Ready control bit
This is the control bit for the /DTR//REQ pin while the pin
is in the DTR mode (selected in WR14). When set, /DTR
is Low; when reset, /DTR is High. This bit is ignored when
/DTR//REQ is programmed to act as a /REQ pin. This bit
is reset by a channel or hardware reset.
Figure 5-7. Write Register 5
D7
D6
D5
D4
D3
D2
D1
D0
Write Register 5
Tx CRC Enable
0 0 Tx 5 Bits(Or Less)/Character
0 1 Tx 7 Bits/Character
1 0 Tx 6 Bits/Character
1 1 Tx 8 Bits/Character
RTS
/SDLC/CRC-16
Tx Enable
Send Break
DTR
UM010901-0601
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