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參數(shù)資料
| 型號(hào)： | Z85230 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁(yè)數(shù)： | 58/317頁(yè) |
| 文件大小： | 3201K |
| 代理商： | Z85230 |
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SCC/ESCC User’s Manual
Interfacing the SCC/ESCC
2-39
2
In the Request mode, /REQ will follow the state of the
transmit buffer even though the transmitter is disabled.
Thus, if /REQ is enabled before the transmitter is enabled,
the DMA may write data to the SCC before the transmitter
is enabled. This does not cause a problem in Asynchro-
nous mode, but may cause problems in Synchronous
modes because the SCC sends data in preference to flags
or sync characters. It may also complicate the CRC initial-
ization, which cannot be done until after the transmitter is
enabled. On the ESCC, this complication can be avoided
in SDLC mode by using the Automatic SDLC Opening Flag
Transmission feature and Auto EOM reset feature which
also resets the transmit CRC. (See section 4.4.1.2 for de-
tails). Applications using other synchronous modes should
enable the transmitter before enabling the /REQ function.
With only one exception, the /REQ pin directly follows the
state of the Transmit FIFO (for ESCC, as programmed by
WR7' D5) in this mode. The one exception occurs in syn-
chronous modes at the end of a CRC transmission. At the
end of a CRC transmission, when the closing flag or sync
character is loaded into the Transmit Shift Register, /REQ
is pulsed High for one PCLK cycle. The DMA uses this fall-
ing edge on /REQ to write the first character of the next
frame to the SCC.
2.5.2.4 DMA Request On Receive
The Request On Receive function is selected by setting D6
and D5 of WR1 to 1 and then enabling the function by set-
ting D7 of WR1 to 1. In this mode, the /W//REQ pin carries
the /REQ signal, which is active Low. When REQ on Re-
ceive is selected, but not yet enabled (WR1 D7=0), the
/W//REQ pin is driven High. When the enable bit is set,
/REQ goes Low if the Receive FIFO contains a character
at the time, or will remain High until a character enters the
Receive FIFO. Note that the /REQ pin follows the state of
the Receive FIFO even though the receiver is disabled.
Thus, if the receiver is disabled and /REQ is still enabled,
the DMA transfers the previously received data correctly.
In this mode, the /REQ pin directly follows the state of the
Receive FIFO with only one exception. /REQ goes Low
when a character enters the Receive FIFO and remains
Low until this character is removed from the Receive FIFO.
The SCC generates only one falling edge on /REQ per
character transfer requested (Figure 2-32). The one ex-
ception occurs in the case of a special receive condition in
the Receive Interrupt on First Character or Special Condi-
tion mode, or the Receive Interrupt on Special Condition
Only mode. In these two interrupt modes, any receive
character with a special receive condition is locked at the
top of the FIFO until an Error Reset command is issued.
This character in the Receive FIFO would ordinarily cause
additional DMA Requests after the first time it is read.
However, the logic in the SCC guarantees only one falling
edge on /REQ by holding /REQ High from the time the
character with the special receive condition is read, and
the FIFO locked, until after the Error Reset command has
been issued.
Figure 2-32. DMA Receive Request Assertion
Read Strobe
to FIFO
Rx Character
Available
W/REQ
(=REQ)
Character Available
FIFO
Empty
UM010901-0601
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