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參數(shù)資料
| 型號： | Z85230 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁數(shù)： | 115/317頁 |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85230 |
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SCC/ESCC User’s Manual
Register Descriptions
5-8
5.1 INTRODUCTION
(Continued)
This bit is internally set to 1 in SDLC mode and the SCC
calculates the CRC on all bits except zeros inserted be-
tween the opening and closing flags. This bit is ignored in
asynchronous modes.
Bit 2: Address Search Mode (SDLC)
Setting this bit in SDLC mode causes messages with ad-
dresses not matching the address programmed in WR6 to
be rejected. No receiver interrupts occur in this mode un-
less there is an address match. The address that the SCC
attempts to match is unique (1 in 256) or multiple (16 in
256), depending on the state of Sync Character Load In-
hibit bit. Address FFH is always recognized as a global ad-
dress. The Address Search mode bit is ignored in all
modes except SDLC.
Bit 1: SYNC Character Load Inhibi
If this bit is set to 1 in any mode except SDLC, the SCC com-
pares the byte in WR6 with the byte about to be stored in the
FIFO, and it inhibits this load if the bytes are equal. (Caution:
this also occurs in the asynchronous mode if the received
character matches the contents of WR6.) The SCC does
not calculate the CRC on bytes stripped from the data
stream in this manner. If the 6-bit sync option is selected
while in Monosync mode, the comparison is still across
eight bits, so WR6 is programmed for proper operation.
t
If the 6-bit sync option is selected with this bit set to 1, all
sync characters except the one immediately preceding the
data are stripped from the message. If the 6-bit sync option
is selected while in the Bisync mode, this bit is ignored.
The address recognition logic of the receiver is modified in
SDLC mode if this bit is set to 1, i.e., only the four most sig-
nificant bits of WR6 must match the receiver address. This
procedure allows the SCC to receive frames from up to 16
separate sources without programming WR6 for each
source (if each station address has the four most signifi-
cant bits in common). The address field in the frame is still
eight bits long. Address FFH is always recognized as a
global address.
The bit is ignored in SDLC mode if Address Search mode
has not been selected.
Bit 0: Receiver Enable
When this bit is set to 1, receiver operation begins. This bit
should be set only after all other receiver parameters are
established and the receiver is completely initialized. This
bit is reset by a channel or hardware reset command, and
it disables the receiver.
5.2.5 Write Register 4 (Transmit/Receive Mis-
cellaneous Parameters and Modes)
WR4 contains the control bits for both the receiver and the
transmitter. These bits should be set in the transmit and
receiver initialization routine before issuing the contents of
WR1, WR3, WR6, and WR7. Bit positions for WR4 are
shown in Figure 5-6. On the ESCC and 85C30, with the
Extended Read option enabled, this register is read as
RR4.
Bits 7 and 6: Clock Rate bits 1 and 0
These bits specify the multiplier between the clock and
data rates. In synchronous modes, the 1X mode is forced
internally and these bits are ignored unless External Sync
mode has been selected.
1X Mode (00).
In External Sync mode, this bit combination specifies that
only the /SYNC pin is used to achieve character synchro-
nization.
The clock rate and data rate are the same.
16X Mode (01).
External Sync mode, this bit combination specifies that only
the /SYNC pin is used to achieve character synchronization.
The clock rate is 16 times the data rate. In
32X Mode (10).
External Sync mode, this bit combination specifies that ei-
ther the /SYNC pin or a match with the character stored in
WR7 will signal character synchronization. The sync char-
acter can be either six or eight bits long as specified by the
6-bit/8-bit sync bit in WR10.
The clock rate is 32 times the data rate. In
Figure 5-6. Write Register 4
D7
D6
D5
D4
D3
D2
D1
D0
Write Register 4
Parity Enable
0 0 X1 Clock Mode
0 1 X16 Clock Mode
1 0 X32 Clock Mode
1 1 X64 Clock Mode
Parity EVEN//ODD
0 0 Sync Modes Enable
0 1 1 Stop Bit/Character
1 0 1 1/2 Stop Bits/Character
1 1 2 Stop Bits/Character
0 0 8-Bit Sync Character
0 1 16-Bit Sync Character
1 0 SDLC Mode (01111110 Flag)
1 1 External Sync Mode
UM010901-0601
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