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| 型號(hào)： | Z85230 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁(yè)數(shù)： | 119/317頁(yè) |
| 文件大小： | 3201K |
| 代理商： | Z85230 |
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SCC/ESCC User’s Manual
Register Descriptions
5-12
5.1 INTRODUCTION
(Continued)
5.2.9 Write Register 7 Prime (ESCC only)
This Register is used only with the ESCC. Write Register
7 Prime is located at the same address as Write Register
7. This register is written to by setting bit D0 of WR15 to a
1. Refer to the description in the section on Write Register
15. Features enabled in WR7 Prime remain enabled
unless otherwise disabled; a hardware or channel reset
leaves WR7 Prime with all features intact (register
contents are 0) (Figure 5-10).
Bit 7: Reserved
This bit is not used and must always be written zero.
Bit 6: Extended Read Enable bit
Setting this bit enables the reading of WR3, WR4, WR5,
WR7 Prime and WR10. When this feature is enabled,
these registers can be accessed by reading RR9, RR4,
RR5, RR14, and RR11, respectively. When the extended
read is not enabled, register access is identical to that of
the NMOS/CMOS version. Refer to Chapter Two on how
this feature affects the mapping of read registers.
Bit 5: Transmit FIFO Interrupt Level
If this bit is set, the transmit buffer empty interrupt is gen-
erated when the Transmit FIFO is completely empty. If this
bit is reset (0), the transmit buffer empty interrupt is gener-
ated when the entry location of the Transmit FIFO is emp-
ty. This latter operation is identical to that of the
NMOS/CMOS version.
In the DMA Request on Transmit Mode, when using either
the /W//REQ or /DTR//REQ pins, the request is asserted
when the Transmit FIFO is completely empty if the Trans-
mit FIFO Interrupt Level bit is set. The request is asserted
when the entry location of the Transmit FIFO is empty if the
Transmit FIFO Interrupt Level bit is reset (0).
Bit 4: /DTR//REQ Timing
If this bit is set and the /DTR//REQ pin is used for Request
Mode (WR14 bit D2 = 1), the deactivation of the
/DTR//REQ pin is identical to the /W//REQ pin. Refer to the
chapter on interfacing for further details. If this bit is reset
(0), the deactivation time for the /DTR//REQ pin is 4TcPc.
This latter operation is identical to that of the SCC.
Bit 3: Receive FIFO Interrupt Level
If WR7' D3=1 and “Receive Interrupt on All Characters and
Special Conditions” is enabled, the Receive Character
Available interrupt is triggered when the Rx FIFO is half full,
i.e., the four byte slots of the Rx FIFO are empty. However,
if any character has a special condition, a special condition
interrupt is generated when the character is loaded into the
Receive FIFO. Therefore, the special condition interrupt
service routine should read RR1 before reading the data to
determine which byte has which special condition.
If WR7' D3=0, the ESCC sets the receiver and generates
the receive character available interrupt on every received
character, regardless of any special receive condition.
Bit 2: Auto /RTS pin Deactivation
This bit controls the timing of the deassertion of the /RTS
pin. If the ESCC is programmed for SDLC mode and Flag-
On-Underrun (WR10 D2=0), this bit is set and the RTS bit
is reset. The /RTS is deasserted automatically at the last
bit of the closing flag, triggered by the rising edge of the
Transmit Clock. If this bit is reset, the /RTS pin follows the
state programmed in WR5 D1.
Bit 1: Automatic EOM Reset
If this bit is set, the ESCC automatically resets the Tx Un-
derrun/EOM latch and presets the transmit CRC generator
to its programmed preset state (per values set in WR5 D2
& WR10 D7). Therefore, it is not necessary to issue the
Reset Tx Underrun/EOM latch command when this feature
is enabled. If this bit is reset, ESCC operation is identical
to the SCC.
Bit 0: Automatic Tx SDLC Flag
If this bit is set, the ESCC automatically transmits an SDLC
flag before transmitting data. This removes the require-
ment to reset the mark idle bit (WR10 D3) before writing
data to the transmitter, or having to enable the transmitter
before writing data to the Transmit FIFO. Also, this feature
enables a transmit data write before enabling the transmit-
ter. If this bit is reset, operation is identical to that of the
SCC.
Figure 5-10. Write Register 7 Prime
D7 D6 D5
D4
D3
D2
D1
D0
WR7'
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Rx FIFO Half Full
DTR/REQ Timing Mode
Tx FIFO Empty
Extended Read Enable
Reserved (Must be 0)
UM010901-0601
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