參數(shù)資料
型號(hào): Z85230
廠商: ZiLOG, Inc.
英文描述: The Zilog SCC Serial Communication Controller
中文描述: Zilog公司鱗癌的串行通信控制器
文件頁(yè)數(shù): 234/317頁(yè)
文件大?。?/td> 3201K
代理商: Z85230
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Application Note
Serial Communication Controller (SCC
): SDLC Mode of Operation
6-99
1
Notes on Figure 3:
1.
The receiver is usually in hunt mode when waiting for
a frame. When the opening flag is received, an
External/Status Interrupt is generated, indicating the
change from hunt mode to sync mode.
2.
The /SYNC output follows the state of the sync register
comparison output. The comparison is done on a bit
by bit basis, so the /SYNC pin is only active for one bit-
time. /SYNC goes active one bit-time after the last bit
of the sync character is sampled at the RxD pin.
3.
A Receive Character Available Interrupt is generated
11 bit-times after the last bit of the character is
sampled at the RxD pin. In this mode, enable the DMA
on this interrupt. This interrupt is for data 81H.
4.
If SCC’s DMA request function has been enabled,
/REQ becomes active here.
5.
DMA request for data 42H.
6.
DMA request for data 0FFH.
7.
DMA request for data 42H.
8.
DMA request for the first CRC byte. The SCC treats
the CRC as data, since the SCC does not yet
distinguish a difference between CRC and data!
9.
DMA request for the second CRC byte. The closing
flag is recognized two bit-times before the second
CRC byte is completely assembled in the Receive
Shift Register. As soon as it is transferred to the
Receive Buffer, it generates a DMA request.
10. This interrupt is EOF (End of Frame), a Special
Condition interrupt. This will not occur until the DMA
has read the 2nd CRC byte from the Receive Buffer.
When it occurs, the Receive Buffer is locked and no
more DMA requests can be generated until the
Receive Buffer is unlocked by issuing the Error Reset
command. Before issuing this command, all of the
status bits required (e.g., the CRC error status) must
be read, and the last two bytes read by the DMA
discarded. The enable interrupt on next Receive
Character command must be sent to the SCC so that
the next character (i.e., the First Character of the next
frame) will produce an interrupt. If this is not done, the
character will generate a DMA request, not an
interrupt.
Should a Special Condition occur within the data
stream (i.e., for a condition other than EOF) the /INT
pin will not go active until the character with the
Special Condition has been read by the DMA.
11. DMA request for 2nd CRC bytes. This occurs when
the EOF interrupt service routine has not disabled the
DMA function of the SCC, and did not read the data
after unlocking the buffer by issuing an Error Reset
command.
12. External/Status Interrupt for the Sync/Hunt change.
This occurs when the SCC recognizes an Abort
(Marking line) and forces the receiver into hunt mode.
The SCC can be programmed so that the Abort itself
generates an interrupt if required. If flag idle was set,
this interrupt would not occur.
UM010901-0601
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