參數(shù)資料
型號(hào)： W972GG8JB-25
廠(chǎng)商： WINBOND ELECTRONICS CORP
元件分類(lèi)： DRAM
英文描述： 256M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 8/86頁(yè)
文件大?。?/td> 1466K
代理商： W972GG8JB-25
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 16 -
Revision A02
7.2.3.1
Extended Mode Register for OCD Impedance Adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs
are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMR bit enabling RDQS
operation. In Drive (1) mode, all DQ, DQS (and RDQS) signals are driven HIGH and all DQS signals
are driven LOW. In Drive (0) mode, all DQ, DQS (and RDQS) signals are driven LOW and all DQS
signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD
calibration default, output driver characteristics have a nominal impedance value of 18
Ω during
nominal temperature and voltage conditions. OCD applies only to normal full strength output drive
setting defined by EMR (1) and if reduced strength is set, OCD default driver characteristics are not
applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are
not applicable. After OCD calibration is completed or driver strength is set to default, subsequent
EMRS commands not intended to adjust OCD chara
cteristics must specify A[9:7] as 000 in order to
maintain the default or calibrated value.
Table 1
– OCD Drive Mode Program
A9
A8
A7
Operation
0
OCD calibration mode exit
0
1
Drive (1) DQ, DQS, (RDQS) HIGH and DQS LOW
0
1
0
Drive (0) DQ, DQS, (RDQS) LOW and
DQS HIGH
1
0
Adjust mode
1
OCD calibration default
7.2.3.2
OCD Impedance Adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a
4 bit burst code to DDR2 SDRAM as in table 2. For this operation, Burst Length has to be set to BL =
4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the
same time. DT0 in table 2 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver
output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all
DQs and DQSs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The
maximum step count for adjustment is 16 and when the limit is reached, further increment or
decrement code has no effect. The default setting may be any step within the 16 step range. When
Adjust mode command is issued, AL from previously set value must be applied.
Table 2
– OCD Adjust Mode Program
4 bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
NOP (No operation)
0
1
Increase by 1 step
NOP
0
1
0
Decrease by 1 step
NOP
0
1
0
NOP
Increase by 1 step
1
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
0
1
0
Decrease by 1 step
Increase by 1 step
1
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Other Combinations
Reserved
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參數(shù)描述
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