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| 型號(hào)： | W972GG8JB-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件頁(yè)數(shù)： | 26/86頁(yè) |
| 文件大?。?/td> | 1466K |
| 代理商： | W972GG8JB-25 |
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W972GG8JB
Publication Release Date: Feb. 18, 2011
- 32 -
Revision A02
8.2
Clock Enable (CKE) Truth Table for Synchronous Transitions
CURRENT
STATE
2
CKE
COMMAND (N)
3
RAS , CAS , WE , CS
ACTION (N)
3
NOTES
Previous Cycle
1
(N-1)
Current Cycle
1
(N)
Power Down
L
X
Maintain Power Down
11, 12, 13
L
H
DESELECT or NOP
Power Down Exit
4, 8, 11, 12
Self Refresh
L
X
Maintain Power Down
11, 13, 14
L
H
DESELECT or NOP
Self Refresh Exit
4, 5, 9, 14
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down
Entry
4, 8, 10, 11,
12
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down
Entry
4, 8, 10, 11,
12
H
L
REFRESH
Self Refresh Entry
6, 9, 11, 12
H
Refer to the Command Truth Table
7
Notes:
1.
CKE (N) is the logic state of CKE at clock edge N; CKE (N
–1) was the state of CKE at the previous clock edge.
2.
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3.
COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4.
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5.
On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period.
Read commands may be issued only after tXSRD (200 clocks) is satisfied.
6.
Self Refresh mode can only be entered from the All Banks Idle state.
7.
Must be a legal command as defined in the Command Truth Table.
8.
Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9.
Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set
operations or Precharge operations are in progress. See section 7.9 "Power Down Mode" and section 7.3.7/7.3.8 "Self
Refresh Entry/Exit Command" for a detailed list of restrictions.
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
12. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 7.9.
13.
“X” means “dont care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven
high or low in Power Down if the ODT function is enabled
(Bit A2 or A6 set to “1” in EMR (1)).
14. VREF must be maintained during Self Refresh operation.
15. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
See section 7.2.4.
16. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode.
8.3
Data Mask (DM) Truth Table
FUNCTION
DM
DQS
NOTE
Write enable
L
Valid
1
Write inhibit
H
X
1
Note:
1. Used to mask write data, provided coincident with the corresponding data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W972GG8JB-25I | 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 80WBGA |
| W972GG8JB-3 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS |
| W9751G6IB-25 | 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W9751G6JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:512GB DDRII |
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