參數(shù)資料
型號(hào)： W972GG8JB-25
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 256M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 19/86頁(yè)
文件大?。?/td> 1466K
代理商： W972GG8JB-25
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 26 -
Revision A02
7.4.5
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM,
consistent with the implementation on DDR1 SDRAM. It has identical timings on write operations as
the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to
insure matched system timing. DM function is disabled, when RDQS / RDQS are enabled by
EMRS(1). (Example timing waveform refer to 10.15 Write operation with Data Mask diagram in
Chapter 10)
7.5
Burst Interrupt
Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by
Write or Precharge Command is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by
Read or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other
Read burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other
Write burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.
6. Read or Write burst with Auto-precharge enabled is not allowed to interrupt.
7. Read burst interruption is allowed by a Read with Auto-precharge command.
8. Write burst interruption is allowed by a Write with Auto-precharge command.
9. All command timings are referenced to burst length set in the mode register. They are not
referenced to the actual burst. For example below:
Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the
mode register and not the actual burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising
clock after the un-interrupted burst end and not from the end of the actual burst end.
(Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in
Chapter 10)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W972GG8JB-25I 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 80WBGA
W972GG8JB-3 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS
W9751G6IB-25 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)
W9751G6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
W9751G6JB-25 制造商:Winbond Electronics Corp 功能描述:512GB DDRII
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