參數(shù)資料
型號(hào)： W972GG8JB-25
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 256M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60
文件頁數(shù)： 57/86頁
文件大小： 1466K
代理商： W972GG8JB-25
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 60 -
Revision A02
44. Data setup and hold time derating.
DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe
DQ
Slew
Rate
(V/nS)
ΔtDS, ΔtDH derating values for DDR2-667, DDR2-800 and DDR2-1066 (All units in pS; the note applies to
the entire table)
DQS/ DQS Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
0.8 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0
100
45
100
45
100
45
-
1.5
67
21
67
21
67
21
79
33
-
1.0
0
12
24
-
0.9
-
-5
-14
-5
-14
7
-2
19
10
31
22
-
0.8
-
-13
-31
-1
-19
11
-7
23
5
35
17
-
0.7
-
-10
-42
2
-30
14
-18
26
-6
38
6
-
0.6
-
-10
-59
2
-47
14
-35
26
-23
38
-11
0.5
-
-24
-89
-12
-77
0
-65
12
-53
0.4
-
-52
-140
-40
-128
-28
-116
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and
tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded VREF(dc) to AC region, use nominal slew rate for derating value. See Figure 24 Illustration of nominal slew rate for
tDS (differential DQS, DQS ).
If the actual signal is later than the
nominal slew rate line anywhere between shaded VREF(dc) to AC region, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 25 Illustration of tangent line
for tDS (differential DQS, DQS ).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded
DC level to VREF(dc) region, use nominal slew rate for derating value. See Figure 26 Illustration of nominal slew rate
for tDH (differential DQS, DQS ).
If the actual signal is earlier than the nominal slew rate line anyw
here between shaded DC to VREF(dc) region, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 27 Illustration of
tangent line for tDH (differential DQS, DQS ).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential
data strobe table, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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