參數(shù)資料
型號(hào)： W972GG8JB-25
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： DRAM
英文描述： 256M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 17/86頁(yè)
文件大?。?/td> 1466K
代理商： W972GG8JB-25
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 24 -
Revision A02
CMD
1
2
3
4
5
6
7
8
9
10
11
12
0
-1
CLK /CLK
DQS/DQS
DQ
AL=2
CL=3
WL=RL-1=4
≥ tRCD
RL=AL+CL=5
Dout0
Din0
Active
A-Bank
Read
A-Bank
Write
A-Bank
Din1
Din2
Din3
Dout1
Dout2 Dout3
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
Figure 14
– Example 1: Read followed by a write to the same bank,
where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4
1
2
3
4
5
6
7
8
9
10
11
12
0
-1
CL=3
WL=RL-1=2
≥ tRCD
RL=AL+CL=3
AL=0
CMD
CLK/CLK
DQ
Dout0
Dout1 Dout2 Dout3
Din0
Din1
Din2
Din3
Write
A-Bank
Read
A-Bank
Active
A-Bank
DQS/DQS
AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
Figure 15
– Example 2: Read followed by a write to the same bank,
where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4
7.4.2
Burst mode operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or
from memory locations (read cycle). The parameters that define how the burst mode will operate are
burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8
bit burst mode, full interleave address ordering is supported, however, sequential address ordering is
nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].
The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless
burst read or write operations are supported.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W972GG8JB-25I 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 80WBGA
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