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參數(shù)資料
| 型號： | SYM53C825AE |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 50/225頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | SYM53C825AE |
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PCI Functional Description
Configuration Registers
3-6
SYM53C825A/53C825AE Data Manual
Memory Read
Multiple Command
T his command is identical to the Memory Read
command except that it additionally indicates that
the master may intend to fetch more than one
cache line before disconnecting. T he SYM3C825A
supports PCI Read Multiple functionality and will
issue Read Multiple commands on the PCI bus
when the Read Multiple Mode is enabled. T his
mode is enabled by setting bit 2 of the DMODE
register (ERMP). If cache mode has been enabled,
a Read Multiple command will be issued on all
read cycles, except op code fetches, when the fol-
lowing conditions have been met:
1. T he CLSE and ERMP bits must be set.
2. T he Cache Line Size register must contain a
legal burst size value (2, 4, 8, 16, 32, 64, or
128) AND that value must be less than or
equal to the DMODE burst size.
3. T he number of bytes to be transferred at the
time a cache boundary has been reached must
be at least twice the full cache line size.
4. T he chip must be aligned to a cache line
boundary.
When these conditions have been met, the chip
will issue a Read Multiple command instead of a
Memory Read during all PCI read cycles.
Burst Size Selection
T he Read Multiple command reads in multiple
cache lines of data in a single bus ownership. T he
number of cache lines to be read is a multiple of
the cache line size as allowed for in the Revision
2.1 of the PCI specification. T he logic will select
the largest multiple of the cache line size based on
the amount of data to transfer, with the maximum
allowable burst size being determined from the
DMODE Burst Size bits and CT EST 5, bit 2.
Read Multiple with Read Line E nabled
When both the Read Multiple and Read Line
modes have been enabled, the Read Line com-
mand will not be issued if the above conditions are
met. Instead, a Read Multiple command will be
issued, even though the conditions for Read Line
have been met.
If the Read Multiple mode is enabled and the Read
Line mode has been disabled, Read Multiple com-
mands will still be issued if the Read Multiple con-
ditions are met.
Unsupported PCI Commands
T he SYM53C825A does not respond to reserved
commands, special cycle, dual address cycle, or
interrupt acknowledge commands as a slave. It will
never generate these commands as a master.
Configuration Registers
T he Configuration registers are accessible only by
the system BIOS during PCI configuration cycles,
and they are not available to the user at any time.
T hese registers can be accessed by SCRIPT S or
the host processor. T he lower 128 bytes hold con-
figuration data while the upper 128 bytes hold the
SYM53C825A operating registers, which are
described in Chapter Five, “Operating Registers.”
Please note that the information about lower and
upper bytes only applies to the SYM53C825A and
not the SYM53C825AE
Note: T he configuration register descriptions
provide general information only, to
indicate which PCI configuration addresses
are supported in the SYM53C825A. For
detailed information, refer to the PCI
Specification.
Figure 3-1 shows the PCI configuration registers
implemented by the SYM53C825A/825AE.
All PCI-compliant devices, such as the
SYM53C825A, must support the Vendor ID,
Device ID, Command, and Status Registers. Sup-
port of other PCI-compliant registers is optional.
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