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參數(shù)資料
| 型號(hào)： | SYM53C825AE |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 47/225頁(yè) |
| 文件大?。?/td> | 1237K |
| 代理商： | SYM53C825AE |
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PCI Functional Description
PCI Cache Mode
SYM53C825A/53C825AE Data Manual
3-3
PCI Cache Mode
T he SYM53C825A supports the PCI specification
for an 8-bit Cache Line Size register located in
PCI configuration space. T he Cache Line Size reg-
ister provides the ability to sense and react to non-
aligned addresses corresponding to cache line
boundaries. In conjunction with the Cache Line
Size register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each soft-
ware enabled or disabled to allow the user full flex-
ibility in using these commands.
Support for PCI
Cache Line Size Register
T he SYM53C825A supports the PCI specification
for an 8-bit Cache Line Size register in PCI config-
uration space; it can sense and react to non-aligned
addresses corresponding to cache line boundaries.
Selection of Cache
Line Size
T he cache logic will select a cache line size based
on the values for the burst size in the DMODE
register, bit 2 in the CT EST 5 register, and the
PCI Cache Line Size register.
Note: T he SYM53C825A will not automatically
use the value in the PCI Cache Line Size
register as the cache line size value. T he
chip scales the value of the Cache Line Size
register down to the nearest binary burst
size allowed by the chip (2, 4, 8, 16, 32, 64,
or 128), compares this value to the burst
size defined by the values of the DMODE
register and bit 2 of the CT EST 5 register,
then selects the smallest as the value for the
cache line size. T he SYM53C825A will use
this value for all burst data transfers.
Alignment
T he SYM53C825A uses the calculated line size
value to monitor the current address for alignment
to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by
using a “smart aligning” scheme. T his means that
it will attempt to use the largest burst size possible
that is less than the cache line size, to reach the
cache boundary quickly with no overflow. T his
process is a stepping mechanism that will step up
to the highest possible burst size based on the cur-
rent address.
T he stepping process begins at a 4-dword bound-
ary. T he SYM53C825A will first try to align to a 4-
dword boundary (0x00, 0x010, 0x020, etc.) by
using single dword transfers (no bursting). Once
this boundary has been reached the chip will evalu-
ate the current alignment to various burst sizes
allowed, and will select the largest possible as the
next burst size, while not exceeding the cache line
size. T he chip will then issue this burst, and re-
evaluate the alignment to various burst sizes, again
selecting the largest possible while not exceeding
the cache line size, as the next burst size. T his step-
ping process continues until the chip reaches the
cache line size boundary or runs out of data. Once
a cache line boundary is reached, the chip will use
the cache line size as the burst size from then on,
except in the case of multiples (explained below).
T he alignment process is finished at this point.
E xample: Cache Line Size - 16,
Current Address = 0x01
T he chip is not aligned to a 4-dword cache bound-
ary (the stepping threshold), so it issues four sin-
gle-dword transfers (the first is a 3-byte transfer).
At address 0x10, the chip is aligned to a 4-dword
boundary, but not aligned to any higher burst size
boundaries that are less than the cache line size.
So, the part will issue a burst of 4. At this point,
the address is 0x20, and the chip will evaluate that
it is aligned not only to a 4-dword boundary, but
also to an 8-dword boundary. It will select the
highest, 8, and burst 8 dwords. At this point, the
address is 0x40, which is a cache line size bound-
ary. Alignment stops, and the burst size from then
on is switched to 16.
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