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SYM53C825A/53C825AE Data Manual
Introduction
SYM53C825A Benefits Summary
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Bursts 2, 4, 8, 16, 32, 64, or 128 dwords across
PCI bus
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Supports 32-bit word data bursts with variable
burst lengths.
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Pre-fetches up to 8 dwords of SCRIPT S
instructions
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Bursts SCRIPT S op code fetches across the
PCI bus
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Performs zero wait-state bus master data bursts
faster than 110 MB/s (@ 33 MHz)
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Supports PCI Cache Line Size register
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Supports PCI Write and Invalidate, Read Line,
and Read Multiple commands
Integration
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3.3V/5V PCI interface
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Full 32-bit PCI DMA bus master
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Can be used as a third-party PCI bus DMA
controller by using Memory to Memory Move
instructions
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High performance SCSI core
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Integrated SCRIPT S processor
Ease of Use
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Up to one megabyte of add-in memory
support for BIOS and SCRIPT S storage
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Direct PCI-to-SCSI connection
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Reduced SCSI development effort
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Easily adapted to the Advanced SCSI Protocol
Interface (ASPI) or the ANSI Common Access
Method (CAM), with SDMS software.
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Compiler-compatible with existing
SYM53C7X X and SYM53C8X X family
SCRIPT S
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Direct connection to PCI, and SCSI
single-ended and differential buses
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Development tools and sample SCSI
SCRIPT S available
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Maskable and pollable interrupts
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Wide SCSI, A or P cable, and up to 16 devices
supported
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T hree programmable SCSI timers:
Select/Reselect, Handshake-to-Handshake,
and General Purpose. T he time-out period is
programmable from 100
μ
s to greater than
25.6 seconds
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SDMS software for complete PC-based
operating system support
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Support for relative jumps
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SCSI Selected As ID bits for responding with
multiple IDs
Flexibility
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High level programming interface (SCSI
SCRIPT S)
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Programs local memory bus FLASH memory
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Big/Little Endian support
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Selectable 88- or 536-byte DMA FIFO for
backward compatibility
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Tailored SCSI sequences execute from main
system RAM or internal SCRIPT S RAM
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Flexible programming interface to tune I/O
performance or to adapt to unique SCSI
devices
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Support for changes in the logical I/O interface
definition
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Low level access to all registers and all SCSI
bus signals
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Fetch, Master, and Memory Access control
pins
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Separate SCSI and system clocks
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Selectable IRQ pin disable bit
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32 additional scratch pad registers
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Ability to route system clock to SCSI clock