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Instruction Set of the I/O Processor
Transfer Control Instructions
6-16
SYM53C825A/825AE Data Manual
Transfer Control
Instructions
First Dword
Bits 31-30 Instruction Type - Transfer Control
Instruction
Bits 29-27 Op Code
T his 3-bit field specifies the type of transfer
control instruction to be executed. All transfer
control instructions can be conditional. T hey
can be dependent on a true/false comparison
of the ALU Carry bit or a comparison of the
SCSI information transfer phase with the
Phase field, and/or a comparison of the First
Byte Received with the Data Compare field.
Each instruction can operate in initiator or tar-
get mode.
Jump Instruction
1. T he SYM53C825A can do a true/false
comparison of the ALU carry bit, or compare
the phase and/or data as defined by the Phase
Compare, Data Compare and True/False bit
fields. If the comparisons are true, the
SYM53C825A loads the DSP register with the
contents of the DSPS register. T he DSP
register now contains the address of the next
instruction.
2. If the comparisons are false, the
SYM53C825A fetches the next instruction
from the address pointed to by the DSP
register, leaving the instruction pointer
unchanged.
Call Instruction
1. T he SYM53C825A can do a true/false
comparison of the ALU carry bit, or compare
the phase and/or data as defined by the Phase
Compare, Data Compare, and True/False bit
fields. If the comparisons are true, the
SYM53C825A loads the DSP register with the
contents of the DSPS register and that address
value becomes the address of the next
instruction.
When the SYM53C825A executes a Call
instruction, the instruction pointer contained
in the DSP register is stored in the T EMP reg-
ister. Since the T EMP register is not a stack
and can only hold one longword, nested call
instructions are not allowed.
2. If the comparisons are false, the
SYM53C825A fetches the next instruction
from the address pointed to by the DSP
register and the instruction pointer is not
modified.
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Jump
Call
Return
Interrupt
Reserved