參數(shù)資料
型號(hào)： SMJ55161
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 16-BIT MULTIPORT VIDEO RAM
中文描述： 262144由16位多端口視頻內(nèi)存
文件頁(yè)數(shù)： 8/64頁(yè)
文件大?。?/td> 1505K
代理商： SMJ55161
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
pin definitions
Table 2. Pin Description Versus Operational Mode
PIN
DRAM
TRANSFER
SAM
A0 – A8
Row, column address
Row address, tap point
CASL
CASU
DQ
Column-address strobe, DQ output enable
Tap-address strobe
DRAM data I/O, write mask
DSF
Block-write enable
Write-mask-register load enable
Color-register load enable
CBR (option reset)
Split-register-transfer enable
RAS
Row-address strobe
Row-address strobe
SE
SQ output enable,
QSF output enable
Serial clock
SC
SQ
Serial-data output
TRG
DQ output enable
Transfer enable
WE
Write enable, write-per-bit enable
QSF
Special-function output
Serial-register status
NC/GND
VCC
VSS
Either make no external connection or tie to system GND (VSS)
5-V supply
Ground
For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground.
address (A0–A8)
Eighteen address bits are required to decode each one of the 262 144 storage cell locations. Nine row-address
bits are set up on pins A0–A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits
are set up on pins A0–A8 and latched onto the chip on the first falling edge of CASx. All addresses must be
stable on or before the falling edge of RAS and the first falling edge of CASx.
During the full-register-transfer read operation, the states of A0–A8 are latched on the falling edge of RAS to
select one of the 512 rows where the transfer occurs. At the first falling edge of CASx, the column-address bits
A0–A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred
to the SAM. The appropriate 8-bit column address (A0–A7) selects one of 256 tap points (starting positions)
for the serial-data output.
During the split-register-transfer read operation, address bit A7 is ignored at the falling edge of CASx. An internal
counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of
the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (A8) selects the DRAM
half row. The remaining seven address bits (A0–A6) are used to select one of 127 possible starting locations
within the SAM. Locations 127 and 255 are not valid tap points.
row-address strobe (RAS)
RAS is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of
RAS. RAS is a control input that latches the states of the row address, WE, TRG, CASL, CASU, and DSF onto
the chip to invoke DRAM and transfer-read functions of the SMJ55161.
相關(guān)PDF資料
PDF描述
SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM
SMJ626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SML-010DT Chip LEDs with reflectors
SML-010FT Chip LEDs with reflectors
SML-010JT Chip LEDs with reflectors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SMJ55166 制造商:TI 制造商全稱:Texas Instruments 功能描述:262144 BY 16-BIT MULTIPORT VIDEO RAM
SMJ55166-75HKCM 制造商:Micross Components 功能描述:DRAM 2KX16 "VIDEO RAM" - Bulk
SMJ5821TS50 制造商:MICRO SEMI 功能描述:New
SMJ5C1008-25JDCM 制造商:Rochester Electronics LLC 功能描述:- Bulk
SMJ5C1008L-25JDCM 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*