參數(shù)資料
型號(hào)： SMJ55161
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 16-BIT MULTIPORT VIDEO RAM
中文描述： 262144由16位多端口視頻內(nèi)存
文件頁(yè)數(shù)： 35/64頁(yè)
文件大?。?/td> 1505K
代理商： SMJ55161
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
’55161-75
MIN
’55161-80
MIN
UNIT
SYMBOL
MAX
MAX
td(RLTH)
td(RLSH)
td(RLCA)
td(GLRH)
td(CLSH)
td(SCTR)
td(THRH)
td(THRL)
td(THSC)
Delay time, RAS low to TRG high (see Note 19)
tRTH
tRSD
tRAD
tROH
tCSD
tTSL
tTRD
tTRP
tTSD
58
60
ns
Delay time, RAS low to first SC high after TRG high (see Note 20)
75
80
ns
Delay time, RAS low to column address valid
15
35
15
40
ns
Delay time, TRG low to RAS high
20
20
ns
Delay time, CASx low to first SC high after TRG high (see Note 20)
23
25
ns
Delay time, SC high to TRG high (see Notes 19 and 20)
5
5
ns
Delay time, TRG high to RAS high (see Note 19)
–10
–10
ns
Delay time, TRG high to RAS low (see Note 21)
55
60
ns
Delay time, TRG high to SC high (see Note 19)
18
20
ns
td(RHMS)
Delay time, RAS high to last (most significant) rising edge of SC before
boundary switch during split-register-transfer read cycles
20
20
ns
td(CLTH)
td(CASH)
Delay time, CASx low to TRG high in real-time-transfer read cycles
tCTH
tASD
15
15
ns
Delay time, column address to first SC in early-load-transfer read cycles
28
30
ns
td(CAGH)
Delay time, column address to TRG high in real-time-transfer read
cycles
tATH
20
20
ns
td(DCL)
td(DGL)
Delay time, data to CASx low
tDZC
tDZO
0
0
ns
Delay time, data to TRG low
0
0
ns
td(MSRL)
Delay time, last (most significant) rising edge of SC to RAS low before
boundary switch during split-register-transfer read cycles
20
20
ns
td(SCQSF)
Delay time, last (127 or 255) rising edge of SC to QSF switching at the
boundary during split-register-transfer read cycles (see Note 22)
tSQD
28
30
ns
td(CLQSF)
Delay time, CASx low to QSF switching in transfer-read cycles
(see Note 22)
tCQD
33
35
ns
td(GHQSF)
Delay time, TRG high to QSF switching in transfer-read cycles
(see Note 22)
tTQD
28
30
ns
td(RLQSF)
Delay time, RAS low to QSF switching in transfer-read cycles
(see Note 22)
tRQD
73
75
ns
trf(MA)
tt
Timing measurements are referenced to VIL MAX and VIH MIN.
NOTES: 19. Real-time-load transfer read or late-load-transfer read cycle only
20. Early-load-transfer read cycle only
21. Full-register-(read) transfer cycles only
22. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is
VOH / VOL = 2 V/0.8 V.
Refresh time interval, memory
tREF
tT
8
8
ms
Transition time
3
50
3
50
ns
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