參數(shù)資料
型號(hào)： SMJ55161
廠(chǎng)商： Texas Instruments, Inc.
英文描述： 262144 BY 16-BIT MULTIPORT VIDEO RAM
中文描述： 262144由16位多端口視頻內(nèi)存
文件頁(yè)數(shù)： 33/64頁(yè)
文件大?。?/td> 1505K
代理商： SMJ55161
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT.
’55161-75
MIN
140
’55161-80
MIN
150
UNIT
SYMBOL
MAX
MAX
tc(rd)
tc(W)
tc(rdW)
tc(P)
tc(RDWP)
tc(TRD)
tc(SC)
tw(CH)
tw(CL)
tw(RH)
tw(RL)
tw(WL)
tw(TRG)
tw(SCH)
tw(SCL)
tw(GH)
tw(RL)P
tsu(CA)
tsu(SFC)
tsu(RA)
tsu(WMR)
tsu(DQR)
tsu(TRG)
tsu(SFR)
tsu(DCL)
tsu(DWL)
tsu(rd)
tsu(WCL)
tsu(WCH)
tsu(WRH)
th(CLCA)
th(SFC)
th(RA)
Timing measurements are referenced to VIL MAX and VIH MIN.
NOTES:
9. Cycle time assumes tt = 3 ns.
10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the transition times, this can require additional
CASx low time [tw(CL)].
11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the transition times, this can require additional
RAS low time [tw(RL)].
Cycle time, read
tRC
tWC
tRMW
tPC
tPRMW
tRC
tSCC
tCPN
tCAS
tRP
tRAS
tWP
ns
Cycle time, write
140
150
ns
Cycle time, read-modify-write
188
200
ns
Cycle time, page-mode read, write
48
50
ns
Cycle time, page-mode read-modify-write
88
90
ns
Cycle time, transfer read
140
150
ns
Cycle time, serial clock (see Note 9)
24
30
ns
Pulse duration, CASx high
10
10
ns
Pulse duration, CASx low (see Note 10)
20
10 000
20
10 000
ns
Pulse duration, RAS high
55
60
ns
Pulse duration, RAS low (see Note 11)
75
10 000
80
10 000
ns
Pulse duration, WE low
13
15
ns
Pulse duration, TRG low
20
20
ns
Pulse duration, SC high
tSC
tSCP
tTP
tRASP
tASC
tFSC
tASR
tWSR
tMS
tTHS
tFSR
tDSC
tDSW
tRCS
tWCS
tCWL
tRWL
tCAH
tCFH
tRAH
9
10
ns
Pulse duration, SC low
9
10
ns
Pulse duration, TRG high
20
20
ns
Pulse duration, RAS low (page mode)
75
100 000
80
100 000
ns
Setup time, column address before CASx low
0
0
ns
Setup time, DSF before CASx low
0
0
ns
Setup time, row address before RAS low
0
0
ns
Setup time, WE before RAS low
0
0
ns
Setup time, DQ before RAS low
0
0
ns
Setup time, TRG high before RAS low
0
0
ns
Setup time, DSF low before RAS low
0
0
ns
Setup time, data valid before CASx low
0
0
ns
Setup time, data valid before WE low
0
0
ns
Setup time, read command, WE high before CASx low
0
0
ns
Setup time, early-write command, WE low before CASx low
0
0
ns
Setup time, WE low before CASx high, write
18
20
ns
Setup time, WE low before RAS high, write
20
20
ns
Hold time, column address after CASx low
13
15
ns
Hold time, DSF after CASx low
15
15
ns
Hold time, row address after RAS low
10
10
ns
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