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參數(shù)資料
| 型號： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. This mode eliminates the time required for row-address setup, row-address hold,
and address multiplex. The maximum RAS low time and CAS page cycle time used determine the number of
columns that can be accessed.
Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55161 to operate at a
higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx
transitions low. A valid column address can be presented immediately after the row-address hold time has been
satisfied, usually well in advance of the falling edge of CASx. In this case, data is obtained after t
a(C)
MAX
(access time from CASx low) if t
a(CA)
MAX (access time from column address) has been satisfied.
refresh
CAS-before-RAS (CBR) refresh
CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external
row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles
are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode.
The CBRN and CBRS refreshes (no reset) do not end the persistent write-per-bit mode or the stop-point mode.
The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh
is completed within the required time period, t
rf(MA)
. The output buffers remain in the high-impedance state
during the CBR refresh cycles regardless of the state of TRG.
hidden refresh
A hidden refresh is accomplished by holding both CASL and CASU low in the DRAM read cycle and cycling
RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR
refresh, the refreshed row addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the
output buffers remain in the high-impedance state to conserve power. Externally-generated addresses must
be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each
row to be refreshed.
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