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| 型號(hào)： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
functional operation description
Table 1 lists the DRAM and SAM functions, summarizing Table 3 and Table 4.
Table 1. DRAM and SAM Functions
RAS FALL
CASx
FALL
ADDRESS
DQ0–DQ15
MNE
CODE
FUNCTION
CASx
TRG
WE
DSF
DSF
RAS
CASx
§
RAS
CASL
CASU
WE
Reserved (do not use)
L
L
L
L
X
X
X
X
X
—
CBR refresh (no reset) and stop-point
set
CBR refresh (option reset)||
L
X
L
H
X
Stop
Point#
X
X
X
X
CBRS
L
X
H
L
X
X
X
X
CBR
CBR refresh (no reset)
L
X
H
H
X
X
X
X
X
CBRN
Full-register-transfer read
H
L
H
L
X
Row
Address
Row
Address
Row
Address
Tap
Point
Tap
Point
Column
Address
Block
Address
A2–A8
X
X
RT
Split-register-transfer read
H
L
H
H
X
X
X
SRT
DRAM write
(nonpersistent write-per-bit)
H
H
L
L
L
Write
Mask
Valid
Data
RWM
DRAM block write
(nonpersistent write-per-bit)
H
H
L
L
H
Row
Address
Write
Mask
Column
Mask
BWM
DRAM write
(persistent write-per-bit)
H
H
L
L
L
Row
Address
Column
Address
Block
Address
A2–A8
X
Valid
Data
RWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Address
X
Column
Mask
BWM
DRAM write (nonmasked)
H
H
H
L
L
Row
Address
Column
Address
Block
Address
A2–A8
X
Valid
Data
RW
DRAM block write (nonmasked)
H
H
H
L
H
Row
Address
X
Column
Mask
BW
Load write-mask register
H
H
H
H
L
Refresh
Address
Refresh
Address
X
X
Write
Mask
Color
Data
LMR
Load color register
H
H
H
H
H
X
X
LCR
Legend:
Col Mask
Write Mask
X
DQ0–DQ15 are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later.
Logic L is selected when either or both CASL and CASU are low.
§The column address and block address are latched on the first falling edge of CASx.
CBRS cycle should be performed immediately after the powerup initialization cycle.
#A0–A3, A8: don’t care; A4–A7: stop-point code
||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
=
=
=
H: Write to address/column enabled
H: Write to I/O enabled
Don’t care
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