參數(shù)資料
型號(hào)： SMJ55161
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 16-BIT MULTIPORT VIDEO RAM
中文描述： 262144由16位多端口視頻內(nèi)存
文件頁(yè)數(shù)： 24/64頁(yè)
文件大?。?/td> 1505K
代理商： SMJ55161
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
load color register (continued)
RAS
CASx
A0–A8
WE
TRG
DSF
DQ0–DQ15
1
2
3
5
6
Load-Write-Mask-Register Cycle
Load-Color-Register Cycle
Persistent Block-Write Cycle
(use loaded write mask)
1
4
Legend:
1. Refresh address
2. Row address
3. Block address (A2–A8) is latched on the first falling edge of CASx.
4. Color-register data
5. Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS.
6. Column-mask data: DQi–DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever
occurs later.
= don’t care
Figure 14. Example of a Persistent Block Write
DRAM-to-SAM transfer operation
During the DRAM-to-SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by TRG being brought low
and WE being held high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of
RAS, determines whether the full-register-transfer read operation or the split-register-transfer read operation
is performed (see Table 4).
Table 4. SAM Function Table
FUNCTION
RAS FALL
CASx
FALL
ADDRESS
DQ0–DQ15
MNE
CODE
CASx
TRG
WE
DSF
DSF
RAS
CASx
RAS
CASx
WE
Full-register-transfer read
H
L
H
L
X
Row
Addr
Tap
Point
X
X
RT
Split-register-transfer read
H
L
H
H
X
Row
Addr
Tap
Point
X
X
SRT
Logic L is selected when either CASL or CASU are low.
X =
don’t care
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