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| 型號： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 44/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
tw(RH)
RAS
CASx
tsu(RA)
A0–
A8
WE
TRG
DSF
DQ0–
DQ15
tw(RL)P
td(RLCH)
td(RLCL)
tw(CL)
tw(CH)
tc(P)
th(RA)
th(RLCA)
tsu(CA)
th(CLCA)
1
2
2
3
tsu(TRG)
th(TRG)
tsu(WMR)
th(RWM)
tsu(SFR)
th(SFR)
tsu(SFC)
tsu(WCH)
tsu(WRH)
tsu(DQR)
th(RDQ)
tsu(DCL)
(see Note B)
th(WLD) (see Note B)
th(RLD)
Row
Column
Column
td(CHRL)
4
5
5
td(RSF)
See Note A
td(RLCA)
td(CLRH)
th(SFC)
tsu(SFC)
th(SFC)
td(CHRL)
tsu(DWL) (see Note B)
tsu(WCH)
tw(WL)
td(CARH)
td(CACH)
th(CLD) (see Note B)
NOTES: A. Referenced to the first falling edge of CASx or the falling edge of WE, whichever occurs later
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. To ensure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late write
feature is used. If the early write-cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling
edge of RAS.
Figure 35. Enhanced-Page-Mode Write-Cycle Timing
Table 10. Enhanced-Page-Mode Write-Cycle State Table
CYCLE
STATE
1
2
3
4
5
Write operation (nonmasked)
L
L
H
Don’t care
Valid data
Write operation with nonpersistent write-per-bit
L
L
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
L
L
Don’t care
Valid data
Load-write mask on either the first falling edge of CASx or the
falling edge of WE, whichever occurs later.
Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx is a don’t care
during this cycle.
H
L
H
Don’t care
Write mask
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