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| 型號： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 22/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
block write (continued)
A set of four columns makes a block, resulting in 128 blocks along one row. Block 0 comprises columns 0 –3,
block 1 comprises columns 4 –7, block 2 comprises columns 8 –11, etc., as shown in Figure 11.
0
1
2
3
4
5
6
7
511
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Columns
Block 0
Block 1
Block 127
. . . . . . . . . . . . . . . . . . . . . .
One Row of 0–511
Figure 11. Block Columns Organization
During block-write cycles, only the seven most significant column addresses (A2–A8) are latched on the first
falling edge of CASx to decode one of the 128 blocks. Address bits A0–A1 are ignored. Each 1M-bit quadrant
has the same block selected.
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first
falling edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper
DRAM DQ bytes to be written. The column-mask data is input via the DQs and is latched on either the first falling
edge of CASx or the falling edge of WE, whichever occurs later. The 16-bit color-data register must be loaded
prior to performing a block write as described below. Refer to the write-per-bit section for details on use of the
write-mask capability, allowing additional performance options.
Example of block write:
Block-write column address
= 110000000 (A0–A8 from left to right)
bit 0
= 1011
= 1110
= 1111
bit 15
Color-data register
Write-mask register
Column-mask register
1011
1111
0000
2nd
Quad
1100
1111
0111
3rd
Quad
0111
1011
1010
4th
Quad
1st
Quad
Column-address bits A0 and A1 are ignored. Block 0 (columns 0 –3) is selected for each 1M-bit quadrant. The
first quadrant has DQ0–DQ2 written with bits 0–2 from the color-data register (101) to all four columns of block
0. DQ3 is not written and retains its previous data due to write-mask-register-bit 3 being 0.
The second quadrant (DQ4–DQ7) has all four columns masked off due to column-mask bits 4–7 being 0 so
that no data is written.
The third quadrant (DQ8–DQ11 ) has its four DQs written with bits 8 –11 from the color-data register (1100) to
columns 1–3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to
column-mask-register-bit 8 being 0.
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